HW-SW Emulation Framework for Temperature-Aware Design in MPSoCs

New tendencies envisage Multi-Processor Systems-On-Chip (MPSoCs) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute multiple applications (games, video), while meeting additional design constraints (energy consumption, time-to-market). Moreover, the rise of temperature in the die for MPSoCs can seriously affect their final performance and reliability. In this paper, we present a new hardware-software emulation framework that allows designers a complete exploration of the thermal behavior of final MPSoC designs early in the design flow. The proposed framework uses FPGA emulation as the key element to model the hardware components of the considered MPSoC platform at multi-megahertz speeds. It automatically extracts detailed system statistics that are used as input to our software thermal library running in a host computer. This library calculates at run-time the temperature of on-chip components, based on the collected statistics from the emulated system and the final floorplan of the MPSoC. This enables fast testing of various thermal management techniques. Our results show speed-ups of three orders of magnitude compared to cycle-accurate MPSoC simulator

Caracterización y optimización térmica de sistemas en chip mediante emulación con FPGAs

Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadores y Automática, leída el 15/06/2012Tablets and smartphones are some of the many intelligent devices that dominate the consumer electronics market. These systems are complex to design as they must execute multiple applications (e.g.: real-time video processing, 3D games, or wireless communications), while meeting additional design constraints, such as low energy consumption, reduced implementation size and, of course, a short time-to-market. Internally, they rely on Multi-processor Systems on Chip (MPSoCs) as their main processing cores, to meet the tight design constraints: performance, size, power consumption, etc. In a bad design, the high logic density may generate hotspots that compromise the chip reliability. This thesis introduces a FPGA-based emulation framework for easy exploration of SoC design alternatives. It provides fast and accurate estimations of performance, power, temperature, and reliability in one unified flow, to help designers tune their system architecture before going to silicon.El estado del arte, en lo que a diseño de chips para empotrados se refiere, se encuentra dominado por los multi-procesadores en chip, o MPSoCs. Son complejos de diseñar y presentan problemas de disipación de potencia, de temperatura, y de fiabilidad. En este contexto, esta tesis propone una nueva plataforma de emulación para facilitar la exploración del enorme espacio de diseño. La plataforma utiliza una FPGA de propósito general para acelerar la emulación, lo cual le da una ventaja competitiva frente a los simuladores arquitectónicos software, que son mucho más lentos. Los datos obtenidos de la ejecución en la FPGA son enviados a un PC que contiene bibliotecas (modelos) SW para calcular el comportamiento (e.g.: la temperatura, el rendimiento, etc...) que tendría el chip final. La parte experimental está enfocada a dos puntos: por un lado, a verificar que el sistema funciona correctamente y, por otro, a demostrar la utilidad del entorno para realizar exploraciones que muestren los efectos a largo plazo que suceden dentro del chip, como puede ser la evolución de la temperatura, que es un fenómeno lento que normalmente requiere de costosas simulaciones software.Depto. de Arquitectura de Computadores y AutomáticaFac. de InformáticaTRUEunpu

A Fast HW/SW FPGABased Thermal Emulation Framework for MultiProcessor SystemonChip

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are complex to design as they must execute multiple complex applications (e.g. video processing, 3D games), while meeting additional design constraints (e.g. energy consumption or time-to-market). Moreover, the rise of temperature in the die for MPSoC components can seriously affect their final performance and reliability. Therefore, mechanisms to efficiently evaluate complete HW/SW MPSoC designs in terms of energy consumption, temperature, performance and other key metrics are needed. In this paper, we present a new HW/SW FPGA-based emulation framework that allows designers to rapidly extract a number of critical statistics from processing cores, memories and interconnection systems being emulated on a FPGA. This information is then used to interact in real-time with a SW thermal model running on a host computer via an Ethernet port. The results show speed-ups of three orders of magnitude compared to cycle-accurate MPSoC simulators, which enable a very fast exploration of a large range of MPSoC design alternatives at the cycle-accurate level. Finally, our HW/SW framework allows designers to test run-time thermal management strategies with real-life inputs without any loss in the performance of the emulated system

Advanced photonic and electronic systems WILGA 2016

Young Researchers Symposium WILGA on Photonics Applications and Web Engineering has been organized since 1998, two times a year. Subject area of the Wilga Symposium are advanced photonic and electronic systems in all aspects: theoretical, design and application, hardware and software, academic, scientific, research, development, commissioning and industrial, but also educational and development of research and technical staff. Each year, during the international Spring edition, the Wilga Symposium is attended by a few hundred young researchers, graduated M.Sc. students, Ph.D. students, young doctors, young research workers from the R&D institutions, universities, innovative firms, etc. Wilga, gathering through years the organization experience, has turned out to be a perfect relevant information exchange platform between young researchers from Poland with participation  of international guests, all active in the research areas of electron and photon technologies, electronics, photonics, telecommunications, automation, robotics and information technology, but also technical physics. The paper summarizes the achievements of the 38th Spring Edition of 2016 WILGA Symposium, organized in Wilga Village Resort owned by Warsaw University of technology

Hardware-Software Integrated Silicon Photonic Systems

Fabrication of integrated photonic devices and circuits in a CMOS-compatible process or foundry is the essence of the silicon photonic platform. Optical devices in this platform are enabled by the high index contrast between silicon and silicon on insulator. These devices offer potential benefits when integrated with existing and emerging high performance microelectronics. Integration of silicon photonics with small footprints and power-efficient and high-bandwidth operation has long been cited as a solution to existing issues in high performance interconnects for telecommunications and data communication. Stemming from this historic application in communications, new applications in sensing arrays, biochemistry, and even entertainment continue to grow. However, for many technologies to successfully adopt silicon photonics and reap the perceived benefits, the silicon photonic platform must extend toward development of a full ecosystem. Such extension includes implementation of low cost and robust electronic-photonic packaging techniques for all applications. In an ecosystem implemented with services ranging from device fabrication all the way to packaged products, ease-of-use and ease-of-deployment in systems that require many hardware and software components becomes possible. With the onset of the Internet of Things (IoT), nearly all technologies—sensors, compute, communication devices, etc.—persist in systems with some level of localized or distributed software interaction. These interactions often require a level of networked communications. For silicon photonics to penetrate technologies comprising IoT, it is advantageous to implement such devices in a hardware-software integrated way. Meaning, all functionalities and interactions related to the silicon photonic devices are well defined in terms of the physicality of the hardware. This hardware is then abstracted into various levels of software as needed in the system. The power of hardware-software integration allows many of the piece-wise demonstrated functionalities of silicon photonics to easily translate to commercial implementation. This work begins by briefly highlighting the challenges and solutions for transforming existing silicon photonic platforms to a full-fledged silicon photonic ecosystem. The highlighted solutions in development consist of tools for fabrication, testing, subsystem packaging, and system validation. Building off the knowledge of a silicon photonic ecosystem in development, this work continues by demonstrating various levels of hardware-software integration. These are primarily focused on silicon photonic interconnects. The first hardware-software integration-focused portion of this work explores silicon microring-based devices as a key building block for greater silicon photonic subsystems. The microring’s sensitivity to thermal fluctuations is identified not as a flaw, but as a tool for functionalization. A logical control system is implemented to mitigate thermal effects that would normally render a microring resonator inoperable. The mechanism to control the microring is extended and abstracted with software programmability to offer wavelength routing as a network primitive. This functionality, available through hardware-software integration, offers the possibility for ubiquitous deployment of such microring devices in future photonic interconnection networks. The second hardware-software integration-focused portion of this work explores dynamic silicon photonic switching devices and circuits. Specifically, interactions with and implications of high-speed data propagation and link layer control are demonstrated. The characteristics of photonic link setup include transients due to physical layer optical effects, latencies involved with initializing burst mode links, and optical link quality. The impacts on the functionalities and performance offered by photonic devices are explored. An optical network interface platform is devised using FPGAs to encapsulate hardware and software for controlling these characteristics using custom hardware description language, firmware, and software. A basic version of a silicon photonic network controller using FPGAs is used as a tool to demonstrate a highly scalable switch architecture using microring resonators. This architecture would not be possible without some semblance of this controller, combined with advanced electronic-photonic packaging. A more advanced deployment of the network interface platform is used to demonstrate a method for accelerating photonic links using out-of-band arbitration. A first demonstration of this platform is performed on a silicon photonic microring router network. A second demonstration is used to further explore the feasibility of full hardware-software integrated photonic device actuation, link layer control, and out-of-band arbitration. The demonstration is performed on a complete silicon photonic network with both spatial switching and wavelength routing functionalities. The aforementioned hardware-software integration mechanisms are rigorously tested for data communications applications. Capabilities are shown for very reliable, low latency, and dynamic high-speed data delivery using silicon photonic devices. Applying these mechanisms to complete electronic-photonic packaged subsystems provides a strong path to commercial manifestations of functional silicon photonic devices

WDM/TDM PON bidirectional networks single-fiber/wavelength RSOA-based ONUs layer 1/2 optimization

This Thesis proposes the design and the optimization of a hybrid WDM/TDM PON at the L1 (PHY) and L2 (MAC) layers, in terms of minimum deployment cost and enhanced performance for Greenfield NGPON. The particular case of RSOA-based ONUs and ODN using a single-fibre/single-wavelength is deeply analysed. In this WDM/TDM PON relevant parameters are optimized. Special attention has been given at the main noise impairment in this type of networks: the Rayleigh Backscattering effect, which cannot be prevented. To understand its behaviour and mitigate its effects, a novel mathematical model for the Rayleigh Backscattering in burst mode transmission is presented for the first time, and it has been used to optimize the WDM/TDM RSOA based PON. Also, a cost-effective, simple design SCM WDM/TDM PON with rSOA-based ONU, was optimized and implemented. This prototype was successfully tested showing high performance, robustness, versatility and reliability. So, the system is able to give coverage up to 1280 users at 2.5 Gb/s / 1.25 Gb/s downstream/upstream, over 20 Km, and being compatible with the GPON ITU-T recommendation. This precedent has enabled the SARDANA network to extend the design, architecture and capabilities of a WDM/TDM PON for a long reach metro-access network (100 km). A proposal for an agile Transmission Convergence sub-layer is presented as another relevant contribution of this work. It is based on the optimization of the standards GPON and XG-PON (for compatibility), but applied to a long reach metro-access TDM/WDM PON rSOA-based network with higher client count. Finally, a proposal of physical implementation for the SARDANA layer 2 and possible configurations for SARDANA internetworking, with the metro network and core transport network, are presented

Control Systems for Silicon Photonic Microring Devices

The continuing growth of microelectronics in speed, scale, and complexity has led to a looming bandwidth bottleneck for traditional electronic interconnects. This has precipitated the penetration of optical interconnects to smaller, more localized scales, in such applications as data centers, supercomputers, and access networks. For this next generation of optical interconnects, the silicon photonic platform has received wide attention for its ability to manifest, more economical, high-performance photonics. The high index contrast and CMOS compatibility of the silicon platform give the potential to intimately integrate small footprint, power-efficient, high-bandwidth photonic interconnects with existing high-performance CMOS microelectronics. Within the silicon photonic platform, traditional photonic elements can be manifested with smaller footprint and higher energy-efficiency. Additionally, the high index contrast allows the successful implementation of silicon microring-based devices, which push the limits on achievable footprint and energy-efficiency metrics. While laboratory demonstrations have testified to their capabilities as powerful modulators, switches, and filters, the commercial implementation of microring-based devices is impeded by their susceptibility to fabrication tolerances and their inherent temperature sensitivity. This work develops and demonstrates methods to resolve the aforementioned sensitivities of microring-based devices. Specifically, the use of integrated heaters to thermally tune and lock microring resonators to laser wavelengths, and the underlying control systems to enable such functionality. The first developed method utilizes power monitoring to show the successful thermal stabilization of a microring modulator under conditions that would normally render it inoperational. In a later demonstration, the photodetector used for power monitoring is co-integrated with the microring modulator, again demonstrating thermal stabilization of a microring modulator and validating the use of defect-enhanced silicon photodiodes for on-chip control systems. Secondly, a generalized method is developed that uses dithering signals to generate anti-symmetric error signals for use in stabilizing microring resonators. A control system utilizing a dithering signal is shown to successfully wavelength lock and thermally stabilize a microring resonator. Characterizations are performed on the robustness and speed of the wavelength locking process when using dithering signals. An FPGA implementation of the control system is used to scale to a WDM microring demultiplexer, demonstrating the simultaneous wavelength locking of multiple microring resonators. Additionally, the dithering technique is adopted to create control systems for microring-based switches, which have traditionally posed a challenging problem due to their multi-state configurations. The aforementioned control systems are rigorously tested for applications with high speed data and analyzed for power efficiency and scalability to show that they can successfully scale to commercial implementations and be the enabling factor in the commercial deployment of microring-based devices

Wave Front Sensing and Correction Using Spatial Modulation and Digitally Enhanced Heterodyne Interferometry

This thesis is about light. Specifically it explores a new way sensing the spatial distribution of amplitude and phase across the wavefront of a propagating laser. It uses spatial light modulators to tag spatially distinct regions of the beam, a single diode to collect the resulting light and digitally enhanced heterodyne interferometry to decode the phase and amplitude information across the wavefront. It also demonstrates how using these methods can be used to maximise the transmission of light through a cavity and shows how minor aberrations in the beam can be corrected in real time. Finally it demonstrate the preferential transmission of higher order modes. Wavefront sensing is becoming increasingly important as the demands on modern interferometers increase. Land based systems such as the Laser Interferometer Gravitational-Wave Observatory (LIGO) use it to maximise the amount of power in the arm cavities during operation and reduce noise, while space based missions such as the Laser Interferometer Space Antenna (LISA) will use it to align distant partner satellites and ensure that the maximum amount of signal is exchanged. Conventionally wavefront sensing is accomplished using either Hartmann Sensors or multi-element diodes. These are well proven and very effective techniques but bring with them a number of well understood limitations. Critically, while they can map a wavefront in detail, they are strictly sensors and can do nothing to correct it. Our new technique is based on a single-element photo-diode and the spatial modulation of the local oscillator beam. We encode orthogonal codes spatially onto this light and use these to separate the phases and amplitudes of different parts of the signal beam in post processing. This technique shifts complexity from the optical hardware into deterministic digital signal processing. Notably, the use of a single analogue channel (photo-diode, connections and analogue to digital converter) avoids some low-frequency error sources. The technique can also sense the wavefront phase at many points, limited only by the number of actuators on the spatial light modulator in contrast to the standard 4 points from a quadrant photo-diode. For ground-based systems, our technique could be used to identify and eliminate higher-order modes, while, for space-based systems, it provides a measure of wavefront tilt which is less susceptible to low frequency noise. In the future it may be possible to couple the technique with an artificial intelligence engine to automate more of the beam alignment process in arrangements involving multiple cavities, preferentially select (or reject) specific higher order modes and start to reduce the burgeoning requirements for human control of these complex instruments

The Star Formation Camera

The Star Formation Camera (SFC) is a wide-field (~15f~19f, \u3e280 arcmin2), highresolution (18~18 mas pixels) UV/optical dichroic camera designed for the Theia 4-m space-borne space telescope concept. SFC will deliver diffraction-limited images at ă \u3e 300 nm in both a blue (190-517nm) and a red (517-1075nm) channel simultaneously. Our aim is to conduct a comprehensive and systematic study of the astrophysical processes and environments relevant for the births and life cycles of stars and their planetary systems, and to investigate and understand the range of environments, feedback mechanisms, and other factors that most affect the outcome of the star and planet formation process. Via a 4-Tier program, we will step out from the nearest star-forming regions within our Galaxy (Tier 1), via the Magellanic Clouds and Local Group galaxies (Tier 2), to other nearby galaxies out to the Virgo Cluster (Tier 3), and on to the early cosmic epochs of galaxy assembly (Tier 4). Each step will build on the detailed knowledge gained at the previous one. This program addresses the origins and evolution of stars, galaxies, and cosmic structure and has direct relevance for the formation and survival of planetary systems like our Solar System and planets like Earth. We present the design and performance specifications resulting from the implementation study of the camera, conducted under NASAfs Astrophysics Strategic Mission Concept Studies program, which is intended to assemble realistic options for mission development over the next decade. The result is an extraordinarily capable instrument that will provide deep, high-resolution imaging across a very wide field enabling a great variety of community science as well as completing the core survey science that drives the design of the camera. The technology associated with the camera is next generation but still relatively high TRL, allowing a low-risk solution with moderate technology development investment over the next 10 years. We estimate the cost of the instrument to be $390M FY08