11,387 research outputs found
Reconfiguration based built-in self-test for analogue front-end circuits
Previous work has shown that it is feasible to implement a fully digital test evaluation function to realise partial self-test on an automatic gain control circuit (AGC). This paper extends the technique to INL, DNL, offset & gain error testing of analogue to digital converters (ADC's). It also shows how the same function can be used to test an AGC / ADC pair. An extension to full self-test is also proposed by the on-chip generation of input stimuli through reconfiguration of existing functions
Digital signature generator for mixed-signal testing
Ponència presentada al 14th IEEE European Test SymposiumEs presenta un nou generador de signatures digitals per controlar dues senyals anàlogues. Es presenta la tecnologia STM 65 nm per demostrar la viabilitat de la proposta.Postprint (published version
Verifying analog circuits based on a digital signature
Verification of analog circuit specifications is a
challenging task requiring expensive test equipment and time
consuming procedures. This paper presents a method for low
cost parameter verification based on statistical analysis of
a digital signature. A CMOS on-chip monitor and sampler
circuit generates the digital signature of the CUT. The monitor
composes two signals (x(t); y(t)) and divides the X-Y plane
with nonlinear boundaries in order to generate a digital code for
every analog (x; y) location. A metric to be used to discriminate
the golden and defective signatures is also proposed. The metric
is based on the definition of a discrepancy factor performing
circuit parameter identification via statistical and pre-training
procedures. The proposed method is applied to verify possible
deviations on the natural frequency of a Biquad filter. Simulation
results show the possibilities of the proposal.Postprint (published version
Analog circuit test based on a digital signature
Production verification of analog circuit specifica-
tions is a challenging task requiring expensive test equipment
and time consuming procedures. This paper presents a method
for low cost on-chip parameter verification based on the analysis
of a digital signature. A 65 nm CMOS on-chip monitor is
proposed and validated in practice. The monitor composes two
signals (x(t), y(t)) and divides the X-Y plane with nonlinear
boundaries in order to generate a digital code for every analog
(x, y) location. A digital signature is obtained using the digital
code and its time duration. A metric defining a discrepancy factor
is used to verify circuit parameters. The method is applied to
detect possible deviations in the natural frequency of a Biquad
filter. Simulated and experimental results show the possibilities
of the proposal.Peer ReviewedPostprint (published version
Spectral Signature Analysis – BIST for RF Front-Ends
In this paper, the Spectral Signature Analysis is presented as a concept for an integrable self-test system (Built-In Self-Test – BIST) for RF front-ends is presented. It is based on modelling the whole RF front-end (transmitter and receiver) on system level, on generating of a Spectral Signature and of evaluating of the Signature Response. Because of using multi-carrier signal as the test signature, the concept is especially useful for tests of linearity and frequency response of front-ends. Due to the presented method of signature response evaluation, this concept can be used for Built-In Self-Correction (BISC) at critical building blocks
Improving the accuracy of RF alternate test using multi-VDD conditions: application to envelope-based test of LNAs
Trabajo presentado al "20 Asina Test Symposium" celebrado en Nueva Delhi (India) del 20 al 23 de Noviembre del 2011.-- Reprinted from (relevant publication info). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the products or services of CSIC Spanish National Research Council, Digital.CSIC. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.This work demonstrates that multi-VDD conditions may be used to improve the accuracy of machine learning mod- els, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90nm CMOS technology. Post- layout simulation results are provided to verify the functionality of the approach. Copyright © 2011 IEEE.This work has been partially funded by a CSIC JAE-Doc contract (cofinanced by FSE), a Spanish MAE-AECID grant and projects: SR2 - Short Range Radio (Catrene European project 2A105SR2 and Avanza I+D Spanish project TSI-020400-2010-55, cofinanced with FEDER program), Auto-calibración y auto-test en circuitos analógicos, mixtos y de
radio frecuencia (Andalusian Government project P09-TIC-5386, cofinanced with FEDER program), and Catrene project TOETS (CT 302).Peer reviewe
Memristor-based Synaptic Networks and Logical Operations Using In-Situ Computing
We present new computational building blocks based on memristive devices.
These blocks, can be used to implement either supervised or unsupervised
learning modules. This is achieved using a crosspoint architecture which is an
efficient array implementation for nanoscale two-terminal memristive devices.
Based on these blocks and an experimentally verified SPICE macromodel for the
memristor, we demonstrate that firstly, the Spike-Timing-Dependent Plasticity
(STDP) can be implemented by a single memristor device and secondly, a
memristor-based competitive Hebbian learning through STDP using a synaptic network. This is achieved by adjusting the memristor's
conductance values (weights) as a function of the timing difference between
presynaptic and postsynaptic spikes. These implementations have a number of
shortcomings due to the memristor's characteristics such as memory decay,
highly nonlinear switching behaviour as a function of applied voltage/current,
and functional uniformity. These shortcomings can be addressed by utilising a
mixed gates that can be used in conjunction with the analogue behaviour for
biomimetic computation. The digital implementations in this paper use in-situ
computational capability of the memristor.Comment: 18 pages, 7 figures, 2 table
A new BIST scheme for low-power and high-resolution DAC testing
A BIST scheme for testing on chip DAC is presented in this paper. We discuss the generation of on chip testing stimuli and the measurement of digital signals with a narrow-band digital filter. We validate the scheme with software simulation and point out the possibility of ADC BIST with verified DACicus-journals
Quality metrics for mixed-signal indirect testing
Postprint (published version
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