A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Energy Efficient Pipeline ADCs Using Ring Amplifiers

Pipeline ADCs require accurate amplification. Traditionally, an operational transconductance amplifier (OTA) configured as a switched-capacitor (SC) amplifier performs such amplification. However, traditional OTAs limit the power efficiency of ADCs since they require high quiescent current for slewing and bandwidth. In addition, it is difficult to design low-voltage OTAs in modern, scaled CMOS. The ring amplifier is an energy efficient and high output swing alternative to an OTA for SC circuits which is basically a three-stage inverter amplifier stabilized in a feedback configuration. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. In this dissertation, three types of innovative ring amplifiers are presented and verified with state-of-the-art energy efficient pipeline ADCs. These new ring amplifiers overcome the limitations of the conventional ring amplifier and further improve energy efficiency. The first topic of this dissertation is a self-biased ring amplifier that makes the ring amplifier more practical and power efficient, while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. In addition, the ring amplifiers are also used as comparators in the 1.5b sub-ADCs by utilizing the unique characteristics of the ring amplifier. This removes the need for dedicated comparators in sub-ADCs, thus further reducing the power consumption of the ADC. The prototype 10.5b 100 MS/s comparator-less pipeline ADC with the self-biased ring amplifiers has measured SNDR, SNR and SFDR of 56.6 dB (9.11b), 57.5 dB and 64.7 dB, respectively, and consumes 2.46 mW, which results in Walden Figure-of-Merit (FoM) of 46.1 fJ/ conversion∙step. The second topic is a fully-differential ring amplifier, which solves the problems of single-ended ring amplifiers while maintaining the benefits of the single-ended ring amplifiers. This differential ring-amplifier is applied in a 13b 50 MS/s SAR-assisted pipeline ADC. Furthermore, an improved capacitive DAC switching method for the first stage SAR reduces the DAC linearity errors and switching energy. The prototype ADC achieves measured SNDR, SNR and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, and consumes 1 mW. This measured performance is equivalent to Walden and Schreier FoMs of 6.9 fJ/conversion∙step and 174.9 dB, respectively. Finally, a four-stage fully-differential ring amplifier improves the small-signal gain to over 90 dB without compromising speed. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. This is more area efficient than the conventional auto-zero noise folding reduction technique. A systematic mismatch free SAR CDAC layout method is also presented. The prototype 15b 100 MS/s calibration-free SAR-assisted pipeline ADC using the four-stage ring amplifier achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in Schreier FoM of 176.6 dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138759/1/yonglim_1.pd

Concepts for smart AD and DA converters

This thesis studies the `smart' concept for application to analog-to-digital and digital-to-analog converters. The smart concept aims at improving performance - in a wide sense - of AD/DA converters by adding on-chip intelligence to extract imperfections and to correct for them. As the smart concept can correct for certain imperfections, it can also enable the use of more efficient architectures, thus yielding an additional performance boost. Chapter 2 studies trends and expectations in converter design with respect to applications, circuit design and technology evolution. Problems and opportunities are identfied, and an overview of performance criteria is given. Chapter 3 introduces the smart concept that takes advantage of the expected opportunities (described in chapter 2) in order to solve the anticipated problems. Chapter 4 applies the smart concept to digital-to-analog converters. In the discussed example, the concept is applied to reduce the area of the analog core of a current-steering DAC. It is shown that a sub-binary variable-radix approach reduces the area of the current-source elements substantially (10x compared to state-of-the-art), while maintaining accuracy by a self-measurement and digital pre-correction scheme. Chapter 5 describes the chip implementation of the sub-binary variable-radix DAC and discusses the experimental results. The results confirm that the sub-binary variable-radix design can achieve the smallest published current-source-array area for the given accuracy (12bit). Chapter 6 applies the smart concept to analog-to-digital converters, with as main goal the improvement of the overall performance in terms of a widely used figure-of-merit. Open-loop circuitry and time interleaving are shown to be key to achieve high-speed low-power solutions. It is suggested to apply a smart approach to reduce the effect of the imperfections, unintentionally caused by these key factors. On high-level, a global picture of the smart solution is proposed that can solve the problems while still maintaining power-efficiency. Chapter 7 deals with the design of a 500MSps open-loop track-and-hold circuit. This circuit is used as a test case to demonstrate the proposed smart approaches. Experimental results are presented and compared against prior art. Though there are several limitations in the design and the measurement setup, the measured performance is comparable to existing state-of-the-art. Chapter 8 introduces the first calibration method that counteracts the accuracy issues of the open-loop track-and-hold. A description of the method is given, and the implementation of the detection algorithm and correction circuitry is discussed. The chapter concludes with experimental measurement results. Chapter 9 introduces the second calibration method that targets the accuracy issues of time-interleaved circuits, in this case a 2-channel version of the implemented track-and-hold. The detection method, processing algorithm and correction circuitry are analyzed and their implementation is explained. Experimental results verify the usefulness of the method

Design of a low power switched-capacitor pipeline analog-to-digital converter

An Analog to Digital Converter (ADC) is a circuit which converts an analog signal into digital signal. Real world is analog, and the data processed by the computer or by other signal processing systems is digital. Therefore, the need for ADCs is obvious. In this thesis, several novel designs used to improve ADCs operation speed and reduce ADC power consumption are proposed. First, a high speed switched source follower (SSF) sample and hold amplifier without feedthrough penalty is implemented and simulated. The SSF sample and hold amplifier can achieve 6 Bit resolution with sampling rate at 10Gs/s. Second, a novel rail-to-rail time domain comparator used in successive approximation register ADC (SAR ADC) is implemented and simulated. The simulation results show that the proposed SAR ADC can only consume 1.3 muW with a 0.7 V power supply. Finally, a prototype pipeline ADC is implemented and fabricated in an IBM 90nm CMOS process. The proposed design is validated using measurement on a fabricated silicon IC, and the proposed 10-bit ADC achieves a peak signal-to-noise- and-distortion-ratio (SNDR) of 47 dB. This SNDR translates to a figure of merit (FOM) of 2.6N/conversion-step with a 1.2 V power supply

The design of calibration circuit for analog-to-digital converter (ADC).

Dua jenis (Jenis 1 dan Jenis 2) litar tentukuran untuk ADC saluran maklumat telah direka bentuk menggunakan kod Verilog-A yang boleh didapati daripada arkib ahdlib dari alat simulasi perisian Cadence Virtuoso. Kod yang diguna pakai telah diubahsuai bagi memenuhi litar tentukuran yang dicadangkan. Dua blok ADC saluran maklumat yang sama (ADC saluran maklumat 1 dan ADC saluran maklumat 2) direalisasi menggunakan 130nm proses Silterra CMOS dengan setiap ADC mempunyai output digital 4-bit masing-masing. Voltan rujukan pada 600mV digunakan dalam operasi ADC saluran maklumat ini dengan bekalan kuasa 1.2V bagi Vdd dan 0V bagi Vss. ADC saluran maklumat beroperasi pada frekuensi pensampelan 2.2727MHz dengan frekuensi input dari DC ke 1.1364 MHz. Julat Voltan input ADC saluran maklumat adalah dari 300 mV ke 900 mV dengan voltan pertengahan pada 600 mV. Peringkat-peringkat saluran maklumat yang digunakan dalam pembinaan kedua-dua ADC saluran maklumat mengunakan litar Pendaraban Digital-ke-Analog Penukar (MDAC). Litar MDAC adalah berdasarkan kepada konfigurasi 1.5-bit suis-kapasitor dengan penguat kendalian (op-amp) pengamiran sepenuhnya yang mempunyai gandaan hampir 2. Pembetulan Ralat Digital (DEC) juga dicadangkan menggunakan kod Verilog-A pada dua blok, pengatur-masa dan penambah 4-bit. Tiada konsep pembetulan secara isyarat digunakan dalam litar tentukuran yang dicadangkan, membolehkan litar MDAC yang sama digunakan tanpa pengubahsuaian. Pejana palsu-rawak (PN) tidak digunakan dalam litar tentukuran yang dicadangkan. INL yang dicapai dengan tentukuran jenis litar 1 adalah dari maksimum 1 LSB ke minimum -1 LSB . Untuk tentukuran jenis litar 2 , INL yang dicapai adalah maksimum 1 LSB dan minimum 0 LSB . DNL yang dicapai dengan jenis 1 adalah dari maksimum 0 LSB ke minimum -1 LSB manakala jenis 2 mencapai 0 LSB . Two types (Type 1 and Type 2) of calibration circuits for the pipelined ADC was desgined using Verilog-A code modeling available from ahdlib Library of the Cadence Virtuoso tool. The modelling codes were modified to suit the proposed calibration circuit. Two identical pipelined ADC blocks (Pipelined ADC 1 and Pipelined ADC 2) were realized in 130nm Silterra CMOS process with each ADC having a 4-bit digital output respectively. A reference voltage of 600mV was used in the operation of the pipelined ADC with power supply connected to 1.2V for Vdd and ground GND for Vss. The pipelined ADC operates at a sampling frequency of 2.2727MHz with input frequency from DC to 1.1364MHz. The input range voltage of the pipelined ADC is 300mV to 900mV with common-mode voltage of 600mV. Stages used in the construction of each pipelined ADCs employed Multiplying Digital-to-Analog Converter (MDAC) circuit architecture. The MDAC circuit is based on the 1.5-bit switched capacitor configuration with fully-differential operational amplifier (op-amp) gain or radix of approximately 2. A Digital Error Correction (DEC) was also proposed using Verilog-A code modeling where two blocks, time-align block and 4-bit adder made up the DEC block. No dithering signal or concept was used in the proposed calibration circuit, enabling the same MDAC circuit to be used with no modifications. A DNL of 0 LSB was achieved when calibration was enabled. The INL achieved by Calibration circuit type 1 is from maximum +1 LSB to minimum -1 LSB. For the Calibration circuit type 2, INL achieved is maximum +1 LSB and minimum 0 LSB. The DNL achieved by type 1 is from maximum 0 LSB to minimum -1 LSB while type 2 achieved 0 LSB

Plasmonic color filter array, high performance analog to digital converter architectures and novel circuit techniques

Part I: Plasmonic color filters can be manufactured at lower cost since they can be fabricated in single lithographic process step as compared to Fabry-Perot based filters. In addition, they have narrow passband making resolving sharp features in sample spectrum possible. Due to these benefits, in this thesis, Plasmonic color filters are investigated as alternative to conventional color filters and their feasibility for spectroscopy demonstrated through reconstruction of 6 sample spectra by using a set of 20 color filters. The error in reconstructed sample spectra is less than 0.137 root mean squared error across all samples. Part II: A novel 12-bit pipelined successive approximation analog to digital converter is investigated for high speed data conversion. The design was implemented in TSMC 65nm process to demonstrate the feasibility of the architecture. Furthermore, a high dynamic range audio delta sigma modulator using pseudo-pseudo differential topology was investigated and feasibility simulated using TSMC 65nm process. In addition, various novel systems and circuit techniques including efficient calibration of feedback digital to analog converters, new boosted switch and push-pull source follower circuits were investigated to improve upon existing circuit topologies

Low Power Analog to Digital Converters in Advanced CMOS Technology Nodes

The dissertation presents system and circuit solutions to improve the power efficiency and address high-speed design issues of ADCs in advanced CMOS technologies. For image sensor applications, a high-performance digitizer prototype based on column-parallel single-slope ADC (SS-ADC) topology for readout of a back-illuminated 3D-stacked CMOS image sensor is presented. To address the high power consumption issue in high-speed digital counters, a passing window (PW) based hybrid counter topology is proposed. To address the high column FPN under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column fixed pattern noise (FPN) of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling (CDS). A single-column digitizer consumes total power of 66.8μW and occupies an area of 5.4 µm x 610 µm. For mobile/wireless receiver applications, this dissertation presents a low-power wide-bandwidth multistage noise-shaping (MASH) continuous-time delta-sigma modulator (CT-ΔΣM) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed MASH 1-1-1 topology is a cascade of three single-loop first-order CT-ΔΣM stages, each of which consists of an active-RC integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulator’s jitter sensitivity performance. FIR’s effect on the noise transfer function (NTF) of the modulator is compensated in the digital domain thanks to the MASH topology. Instead of employing a conventional analog direct feedback path, a 1.5-bit EELU quantizer based on multiplexing comparator outputs is proposed; this approach is suitable for highspeed operation together with power and area benefits. Fabricated in a 40-nm low-power CMOS technology, the modulator’s prototype achieves a 67.3 dB of signal-to-noise and distortion ratio (SNDR), 68 dB of signal-to-noise ratio (SNR), and 68.2 dB of dynamic range (DR) within 50.5 MHz of bandwidth (BW), while consuming 19 mW of total power (P). The proposed modulator features 161.5 dB of figure-of-merit (FOM), defined as FOM = SNDR + 10 log10 (BW/P)

Methodology for testing high-performance data converters using low-accuracy instruments

There has been explosive growth in the consumer electronics market during the last decade. As the IC industry is shifting from PC-centric to consumer electronics-centric, digital technologies are no longer solving all the problems. Electronic devices integrating mixed-signal, RF and other non-purely digital functions are becoming new challenges to the industry. When digital testing has been studied for long time, testing of analog and mixed-signal circuits is still in its development stage. Existing solutions have two major problems. First, high-performance mixed-signal test equipments are expensive and it is difficult to integrate their functions on chip. Second, it is challenging to improve the test capability of existing methods to keep up with the fast-evolving performance of mixed-signal products demanded on the market. The International Technology Roadmap for Semiconductors identified mixed-signal testing as one of the most daunting system-on-a-chip challenges;My works have been focused on developing new strategies for testing the analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Different from conventional methods that require test instruments to have better performance than the device under test, our algorithms allow the use of medium and low-accuracy instruments in testing. Therefore, we can provide practical and accurate test solutions for high-performance data converters. Meanwhile, the test cost is dramatically reduced because of the low price of such test instruments. These algorithms have the potential for built-in self-test and can be generalized to other mixed-signal circuitries. When incorporated with self-calibration, these algorithms can enable new design techniques for mixed-signal integrated circuits. Following contents are covered in the dissertation:;(1) A general stimulus error identification and removal (SEIR) algorithm that can test high-resolution ADCs using two low-linearity signals with a constant offset in between; (2) A center-symmetric interleaving (CSI) strategy for generating test signals to be used with the SEIR algorithm; (3) An architecture-based test algorithm for high-performance pipelined or cyclic ADCs using a single nonlinear stimulus; (4) Using Kalman Filter to improve the efficiency of ADC testing; and (5) A testing algorithm for high-speed high-resolution DACs using low-resolution ADCs with dithering

Ring Amplifier Optimized for High Resolution Analog-to-Digital Converter Applications

In recent years, SAR ADCs have been shown to acheive faster conversion times and improved power efficiencies due to their simple building blocks that are digital in nature and scale favorably with technology. High resolution ADCs with stringent noise requirement has led to the adoption of hybrid ADC architectures such as the two-step SAR. The two-step SAR ADC, also known as pipelined SAR ADC, combine the concepts of SAR and Pipeline ADC architecture where a residue amplifier provides a critical amplification step. An amplifier architecture well suited for residue amplification known as Ring Amplifier (RAMP) has enabled power efficient two-step SAR ADCs. However, RAMP based ADCs with greater than 14 bits of resolution has not been attempted in previous literature. In this work, the design and measurement of a high-resolution two-step SAR ADC utilizing an enhanced RAMP is demonstrated. Additional circuit techniques are introduced that contribute to the energy-efficiency of the ADC. The ADC implemented in 0.18$\mu$m technology achieves a DR of 95dB and a Schreier FOM better than 180dB at both 2MS/s and 15MS/s