Etude des cellules mémoires résistives RRAM à base de HfO2 par caractérisation électrique et simulations atomistiques

Among non-volatile memory technologies, NAND Flash represents a significant portion in the IC market and has benefitted from the traditional scaling of semiconductor industry allowing its high density integration. However, this scaling seems to be problematic beyond the 22 nm node. In an effort to go beyond this scaling limitation, alternative memory solutions are proposed among which Resistive RAM (RRAM) stands out as a serious candidate for NAND Flash replacement. Hence, in this PhD thesis we try to respond to many open questions about RRAM devices based on hafnium oxide (HfO2), in particular, by addressing the lack of detailed physical comprehension about their operation and reliability. The impact of scaling, the role of electrodes, the process of defects formation and diffusion are investigated. The impact of alloying/doping HfO2 with other materials for improved RRAM performance is also studied. Finally, our study attempts to provide some answers on the conductive filament formation, its stability and possible composition.La mémoire NAND Flash représente une part importante dans le marché des circuits intégrés et a bénéficié de la traditionnelle miniaturisation de l’industrie des sémiconducteurs lui permettant un niveau d’intégration élevé. Toutefois, cette miniaturisation semble poser des sérieux problèmes au-delà du noeud 22 nm. Dans un souci de dépasser cette limite, des solutions mémoires alternatives sont proposées parmi lesquelles la mémoire résistive (RRAM) se pose comme un sérieux candidat pour le remplacement de NAND Flash. Ainsi, dans cette thèse nous essayons de répondre à des nombreuses questions ouvertes sur les dispositifs RRAM à base d’oxyde d’hafnium (HfO2) en particulier en adressant le manque de compréhension physique détaillée sur leur fonctionnement et leur fiabilité. L’impact de la réduction de taille des RRAM, le rôle des électrodes et le processus de formation et de diffusion des défauts sont étudiés. L’impact de l’alliage/dopage de HfO2 avec d’autres matériaux pour l’optimisation des RRAM est aussi abordé. Enfin, notre étude tente de donner quelques réponses sur la formation du filament conducteur, sa stabilité et sa possible composition

On the Production Testing of Memristor Ratioed Logic (MRL) Gates

Abstract This paper focuses on the production testing of Memristor Ratioed Logic (MRL) gates. MRL is a family that uses memristors along with CMOS inverters to design logic gates. Two-input NAND and NOR gates are investigated using the stuck at fault model for the memristors and the five-fault model for the transistors. Test escapes may take place while testing faults in the memristors. Therefore, two solutions are proposed to obtain full coverage for the MRL NAND and NOR gates. The first is to apply scaled input voltages and the second is to change the switching threshold of the CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration. It is proven that three ordered test vectors are needed for full coverage in MRL NAND and NOR gates, which is different from the order required to obtain 100% coverage in the conventional NAND and NOR CMOS designs

DESIGN AND TEST OF DIGITAL CIRCUITS AND SYSTEMS USING CMOS AND EMERGING RESISTIVE DEVICES

The memristor is an emerging nano-device. Low power operation, high density, scalability, non-volatility, and compatibility with CMOS Technology have made it a promising technology for memory, Boolean implementation, computing, and logic systems. This dissertation focuses on testing and design of such applications. In particular, we investigate on testing of memristor-based memories, design of memristive implementation of Boolean functions, and reliability and design of neuromorphic computing such as neural network. In addition, we show how to modify threshold logic gates to implement more functions. Although memristor is a promising emerging technology but is prone to defects due to uncertainties in nanoscale fabrication. Fast March tests are proposed in Chapter 2 that benefit from fast write operations. The test application time is reduced significantly while simultaneously reducing the average test energy per cell. Experimental evaluation in 45 nm technology show a speed-up of approximately 70% with a decrease in energy by approximately 40%. DfT schemes are proposed to implement the new test methods. In Chapter 3, an Integer Linear Programming based framework to identify current-mode threshold logic functions is presented. It is shown that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of existing threshold functions is reduced when comparing to the traditional CMOS-based threshold logic implementation. In Chapter 4, a new method to implement threshold logic functions using memristors is presented. This method benefits from the high range of memristor’s resistivity which is used to define different weight values, and reduces significantly the transistor count. The proposed approach implements many more functions as threshold logic gates when comparing to existing implementations. Experimental results in 45 nm technology show that the proposed memristive approach implements threshold logic gates with less area and power consumption. Finally, Chapter 5 focuses on current-based designs for neural networks. CMOS aging impacts the total synaptic current and this impacts the accuracy. Chapter 5 introduces an enhanced memristive crossbar array (MCA) based analog neural network architecture to improve reliability due to the aging effect. A built-in current-based calibration circuit is introduced to restore the total synaptic current. The calibration circuit is a current sensor that receives the ideal reference current for non-aged column and restores the reduced sensed current at each column to the ideal value. Experimental results show that the proposed approach restores the currents with less than 1% precision, and the area overhead is negligible

Physics-based modeling approaches of resistive switching devices for memory and in-memory computing applications

The semiconductor industry is currently challenged by the emergence of Internet of Things, Big data, and deep-learning techniques to enable object recognition and inference in portable computers. These revolutions demand new technologies for memory and computation going beyond the standard CMOS-based platform. In this scenario, resistive switching memory (RRAM) is extremely promising in the frame of storage technology, memory devices, and in-memory computing circuits, such as memristive logic or neuromorphic machines. To serve as enabling technology for these new fields, however, there is still a lack of industrial tools to predict the device behavior under certain operation schemes and to allow for optimization of the device properties based on materials and stack engineering. This work provides an overview of modeling approaches for RRAM simulation, at the level of technology computer aided design and high-level compact models for circuit simulations. Finite element method modeling, kinetic Monte Carlo models, and physics-based analytical models will be reviewed. The adaptation of modeling schemes to various RRAM concepts, such as filamentary switching and interface switching, will be discussed. Finally, application cases of compact modeling to simulate simple RRAM circuits for computing will be shown

On the production testing of analog and digital circuits

This thesis focuses on the production testing of Analog and Digital circuits. First, it addresses the issue of finding a high coverage minimum test set for the second generation current conveyor as this was not tackled before. The circuit under test is used in active capacitance multipliers, V-I scalar circuits, Biquadratic filters and many other applications. This circuit is often used to implement voltage followers, current followers and voltage to current converters. Five faults are assumed per transistor. It is shown that, to obtain 100% fault coverage, the CCII has to be operated in voltage to current converter mode. Only two test values are required to obtain this fault coverage. Additionally, the thesis focuses on the production testing of Memristor Ratioed Logic (MRL) gates because this was not studied before. MRL is a family that uses memristors along with CMOS inverters to design logic gates. Two-input NAND and NOR gates are investigated using the stuck at fault model for the memristors and the five-fault model for the transistors. It is shown that in order to obtain full coverage for the MRL NAND and NOR gates, two solutions are proposed. The first is the usage of scaled input voltages to prevent the output from falling in the undefined region. The second proposed solution is changing the switching threshold VM of the CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration. It is proven that three ordered test vectors are needed for full coverage in MRL NAND and NOR gates, which is different from the 100% coverage test set in the conventional NAND and NOR CMOS designs

Memristive crossbars as hardware accelerators: modelling, design and new uses

Digital electronics has given rise to reliable, affordable, and scalable computing devices. However, new computing paradigms present challenges. For example, machine learning requires repeatedly processing large amounts of data; this creates a bottleneck in conventional computers, where computing and memory are separated. To add to that, Moore’s “law” is plateauing and is thus unlikely to address the increasing demand for computational power. In-memory computing, and specifically hardware accelerators for linear algebra, may address both of these issues. Memristive crossbar arrays are a promising candidate for such hardware accelerators. Memristive devices are fast, energy-efficient, and—when arranged in a crossbar structure—can compute vector-matrix products. Unfortunately, they come with their own set of limitations. The analogue nature of these devices makes them stochastic and thus less reliable compared to digital devices. It does not, however, necessarily make them unsuitable for computing. Nevertheless, successful deployment of analogue hardware accelerators requires a proper understanding of their drawbacks, ways of mitigating the effects of undesired physical behaviour, and applications where some degree of stochasticity is tolerable. In this thesis, I investigate the effects of nonidealities in memristive crossbar arrays, introduce techniques of minimising those negative effects, and present novel crossbar circuit designs for new applications. I mostly focus on physical implementations of neural networks and investigate the influence of device nonidealities on classification accuracy. To make memristive neural networks more reliable, I explore committee machines, rearrangement of crossbar lines, nonideality-aware training, and other techniques. I find that they all may contribute to the higher accuracy of physically implemented neural networks, often comparable to the accuracy of their digital counterparts. Finally, I introduce circuits that extend dot product computations to higher-rank arrays, different linear algebra operations, and quaternion vectors and matrices. These present opportunities for using crossbar arrays in new ways, including the processing of coloured images

OXIDE-BASED MEMRISTIVE DEVICES BY BLOCK COPOLYMER SELF-ASSEMBLY

Oxide-based memristive systems represent today an emerging class of devices with a significant potential in memory, logic, and neuromorphic circuit applications. These devices have a simple capacitor structure and promise superior scalability together with favorable memory performances. This thesis presents a study of resistive switching phenomena in HfOx-based nanoscale memristive devices, with focus on material properties and development of bottom-up approaches for the fabrication of structures with dimension down to the nanoscale. One of the main issues for practical applications regarding device variability is first assessed by doping hafnium oxide films with different concentrations of aluminum atoms. Testing devices are analyzed by physico-chemical and electrical techniques in order to define the effect of oxide doping on the device properties. In the following part of the thesis, the scalability limit is explored in very high density arrays of nanodevices produced exploiting a lithographic approach based on the bottom-up self-assembly of block copolymer templates. This technique allows a tight control over the size and density of the defined features, and the possibilities offered by block copolymer patterning are here discussed. Electrical measurements of the nanodevices are performed through conductive atomic force microscopy. The device variability is examined and related to the inherent oxide non-homogeneity at the nanoscale, while a non-volatile switching of the resistance of the nanodevices is demonstrated. Further, this analysis draws the attention to a crosstalk phenomenon occurring at the nanoscale in a continuous thin film geometry. This result suggests to select different system configurations. A promising technique based on selective reactions with one copolymer block is finally discussed which allows the direct production of oxide patterns from block copolymer templates avoiding a pattern transfer process. In conclusion, the results reported in this thesis highlight the high scalability potential of oxide-based memristive devices, providing a missing piece of information for the understanding and practical development of very high density arrays

Local Characterization of Resistance Switching Phenomena in Transition Metal Oxides

The development of neuromorphic computing systems that emulate the analog charge states and plasticity of the brain’s neuron-synapse architecture has been a major driver of resistance switching materials exploration. Materials that demonstrate changes in conductance with tunable ratios and volatility of resistance states within a single layer are highly desirable. Although excellent resistance switching device performance has been demonstrated in a range of transition metal oxides, a lack of understanding of the fundamental microscale evolution of a material during resistance switching presents a key limitation to controlling switching parameters. Here, we examine the role of materials defects on local resistance switching structures in two representative transition metal oxide materials: HfOv2 thin films and hydrothermally synthesized VOv2 single crystals. In each material, we seek to clarify the structure of resistance switching domains and the kinetics of domain formation resulting from intentional defect introduction. This thesis is therefore divided into two main parts concerning (1) the introduction of planar defects in HfOv2 filamentary resistance switching devices, and (2) the impact of introduction of point defects on the metal-insulator transition in VOv2 single crystals. Part I (Sections 2 – 3) details investigation of Cu ion migration rates in Cu/HfOv2/p+Si and Cu/HfOv2/TiN devices in which oxide microstructure varies between amorphous, polycrystalline, and oriented polycrystalline. Ion migration across the oxide layer is shown to be rate limiting and faster in polycrystalline layers than in amorphous HfO2 layers at equivalent electric field. Moreover, the 3D shape of conductive filaments is investigated by a scribing atomic force microscopy experiment in Cu/HfOv2/p+Si devices and reveals a broad range of filament shapes under identical electrical stress conditions. Thermal dissipation is interpreted as the principal determinant of filament area, while oxide microstructure is shown to direct the location of filaments within the device. In part II (Sections 4 – 5), the hysteresis of the metal-insulator transition (switching volatility) in VOv2 is shown to intrinsically derive from nucleation limited transformations in individual particles. Here, hysteresis is a strong function of particle size, but may be increased or decreased by synthesis techniques that affect the concentration and potency of intrinsic point defects. Upon chemical doping with boron at interstitial lattice sites, a unique kinetic effect on the hysteresis of the current driven metal-insulator transition in two terminal BxVOv2 devices is observed. Dependence of the critical switching current on thermal relaxation time and temperature is characterized and recommendations for further kinetic testing are made. Finally, a few experimental extensions of the work presented in this thesis are made in Section 6

Roadmap on ferroelectric hafnia- and zirconia-based materials and devices

Ferroelectric hafnium and zirconium oxides have undergone rapid scientific development over the last decade, pushing them to the forefront of ultralow-power electronic systems. Maximizing the potential application in memory devices or supercapacitors of these materials requires a combined effort by the scientific community to address technical limitations, which still hinder their application. Besides their favorable intrinsic material properties, HfO2–ZrO2 materials face challenges regarding their endurance, retention, wake-up effect, and high switching voltages. In this Roadmap, we intend to combine the expertise of chemistry, physics, material, and device engineers from leading experts in the ferroelectrics research community to set the direction of travel for these binary ferroelectric oxides. Here, we present a comprehensive overview of the current state of the art and offer readers an informed perspective of where this field is heading, what challenges need to be addressed, and possible applications and prospects for further development