Design of sequences with good correlation properties

This thesis is dedicated to exploring sequences with good correlation properties. Periodic sequences with desirable correlation properties have numerous applications in communications. Ideally, one would like to have a set of sequences whose out-of-phase auto-correlation magnitudes and cross-correlation magnitudes are very small, preferably zero. However, theoretical bounds show that the maximum magnitudes of auto-correlation and cross-correlation of a sequence set are mutually constrained, i.e., if a set of sequences possesses good auto-correlation properties, then the cross-correlation properties are not good and vice versa. The design of sequence sets that achieve those theoretical bounds is therefore of great interest. In addition, instead of pursuing the least possible correlation values within an entire period, it is also interesting to investigate families of sequences with ideal correlation in a smaller zone around the origin. Such sequences are referred to as sequences with zero correlation zone or ZCZ sequences, which have been extensively studied due to their applications in 4G LTE and 5G NR systems, as well as quasi-synchronous code-division multiple-access communication systems. Paper I and a part of Paper II aim to construct sequence sets with low correlation within a whole period. Paper I presents a construction of sequence sets that meets the Sarwate bound. The construction builds a connection between generalised Frank sequences and combinatorial objects, circular Florentine arrays. The size of the sequence sets is determined by the existence of circular Florentine arrays of some order. Paper II further connects circular Florentine arrays to a unified construction of perfect polyphase sequences, which include generalised Frank sequences as a special case. The size of a sequence set that meets the Sarwate bound, depends on a divisor of the period of the employed sequences, as well as the existence of circular Florentine arrays. Paper III-VI and a part of Paper II are devoted to ZCZ sequences. Papers II and III propose infinite families of optimal ZCZ sequence sets with respect to some bound, which are used to eliminate interference within a single cell in a cellular network. Papers V, VI and a part of Paper II focus on constructions of multiple optimal ZCZ sequence sets with favorable inter-set cross-correlation, which can be used in multi-user communication environments to minimize inter-cell interference. In particular, Paper~II employs circular Florentine arrays and improves the number of the optimal ZCZ sequence sets with optimal inter-set cross-correlation property in some cases.Doktorgradsavhandlin

Chip and Signature Interleaving in DS CDMA Systems

Siirretty Doriast

Asynchronous techniques for system-on-chip design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed

Efficient complementary sequences-based architectures and their application to ranging measurements

Premio Extraordinario de Doctorado de la UAH en 2015En las últimas décadas, los sistemas de medición de distancias se han beneficiado de los avances en el área de las comunicaciones inalámbricas. En los sistemas basados en CDMA (Code-Division Multiple-Access), las propiedades de correlación de las secuencias empleadas juegan un papel fundamental en el desarrollo de dispositivos de medición de altas prestaciones. Debido a las sumas ideales de correlaciones aperiódicas, los conjuntos de secuencias complementarias, CSS (Complementary Sets of Sequences), son ampliamente utilizados en sistemas CDMA. En ellos, es deseable el uso de arquitecturas eficientes que permitan generar y correlar CSS del mayor número de secuencias y longitudes posibles. Por el término eficiente se hace referencia a aquellas arquitecturas que requieren menos operaciones por muestra de entrada que con una arquitectura directa. Esta tesis contribuye al desarrollo de arquitecturas eficientes de generación/correlación de CSS y derivadas, como son las secuencias LS (Loosely Synchronized) y GPC (Generalized Pairwise Complementary), que permitan aumentar el número de longitudes y/o de secuencias disponibles. Las contribuciones de la tesis pueden dividirse en dos bloques: En primer lugar, las arquitecturas eficientes de generación/correlación para CSS binarios, derivadas en trabajos previos, son generalizadas al alfabeto multinivel (secuencias con valores reales) mediante el uso de matrices de Hadamard multinivel. Este planteamiento tiene dos ventajas: por un lado el aumento del número de longitudes que pueden generarse/correlarse y la eliminación de las limitaciones de las arquitecturas previas en el número de secuencias en el conjunto. Por otro lado, bajo ciertas condiciones, los parámetros de las arquitecturas generalizadas pueden ajustarse para generar/correlar eficientemente CSS binarios de mayor número de longitudes que con las arquitecturas eficientes previas. En segundo lugar, las arquitecturas propuestas son usadas para el desarrollo de nuevos algoritmos de generación/correlación de secuencias derivadas de CSS que reducen el número de operaciones por muestra de entrada. Finalmente, se presenta la aplicación de las secuencias estudiadas en un nuevo sistema de posicionamiento local basado en Ultra-Wideband y en un sistema de posicionamiento local basado en ultrasonidos

Sequences design for OFDM and CDMA systems

With the emergence of multi-carrier (MC) orthogonal frequency division multiplexing (OFDM) scheme in the current WLAN standards and next generation wireless broadband standards, the necessitation to acquire a method for combating high peak to average power ratio (PMEPR) becomes imminent. In this thesis, we will explore various sequences to determine their PMEPR behaviours, in hopes to find some sequences which could potentially be suitable for PMEPR reduction control under MC system settings. These sequences include $m$ sequences, Sidelnikov sequences, new sequences, Golay sequences, FZC sequences and Legendre sequences. We will also examine the merit factor properties of these sequences, and then we will derive a bound between PMEPR and merit factor. Moreover, in the design of code division multiple access (CDMA) spreading sequence sets, it is critical that each sequence in the set has low autocorrelations and low cross-correlation with other sequences in the same set. In the thesis, we will present a class of GDJ Golay sequences which contains a large zero autocorrelation zone (ZACZ), which could satisfy the low autocorrelation requirement. This class of Golay sequences could potentially be used to construct new CDMA spreading sequence sets

A low-power quadrature digital modulator in 0.18um CMOS

Quadrature digital modulation techniques are widely used in modern communication systems because of their high performance and flexibility. However, these advantages come at the cost of high power consumption. As a result, power consumption has to be taken into account as a main design factor of the modulator.In this thesis, a low-power quadrature digital modulator in 0.18um CMOS is presented with the target system clock speed of 150 MHz. The quadrature digital modulator consists of several key blocks: quadrature direct digital synthesizer (QDDS), pulse shaping filter, interpolation filter and inverse sinc filter. The design strategy is to investigate different implementations for each block and compare the power consumption of these implementations. Based on the comparison results, the implementation that consumes the lowest power will be chosen for each block. First of all, a novel low-power QDDS is proposed in the thesis. Power consumption estimation shows that it can save up to 60% of the power consumption at 150 MHz system clock frequency compared with one conventional design. Power consumption estimation results also show that using two pulse shaping blocks to process I/Q data, cascaded integrator comb (CIC) interpolation structure, and inverse sinc filter with modified canonic signed digit (MCSD) multiplication consume less power than alternative design choices. These low-power blocks are integrated together to achieve a low-power modulator. The power consumption estimation after layout shows that it only consumes about 95 mW at 150 MHz system clock rate, which is much lower than similar commercial products. The designed modulator can provide a low-power solution for various quadrature modulators. It also has an output bandwidth from 0 to 75 MHz, configurable pulse shaping filters and interpolation filters, and an internal sin(x)/x correction filter

Multi-carrier CDMA using convolutional coding and interference cancellation

SIGLEAvailable from British Library Document Supply Centre-DSC:DXN016251 / BLDSC - British Library Document Supply CentreGBUnited Kingdo