Voltage-to-Time Converter for High-Speed Time-Based Analog-to-Digital Converters

In modern complementary metal oxide semiconductor (CMOS) technologies, the supply voltage scales faster than the threshold voltage (Vth) of the transistors in successive smaller nodes. Moreover, the intrinsic gain of the transistors diminishes as well. Consequently, these issues increase the difficulty of designing higher speed and larger resolution analog-to-digital converters (ADCs) employing voltage-domain ADC architectures. Nevertheless, smaller transistor dimensions in state-of-the-art CMOS technologies leads to reduced capacitance, resulting in lower gate delays. Therefore, it becomes beneficial to first convert an input voltage to a 'time signal' using a voltage-to-time converter (VTC), instead of directly converting it into a digital output. This 'time-signal' could then be converted to a digital output through a time-to-digital converter (TDC) for complete analog-to-digital conversion. However, the overall performance of such an ADC will still be limited to the performance level of the voltage-to-time conversion process. Hence, this thesis presents the design of a linear VTC for a high-speed time-based ADC in 28 nm CMOS process. The proposed VTC consists of a sample-and-hold (S/H) circuit, a ramp generator and a comparator to perform the conversion of the input signal from the voltage to the time domain. Larger linearity is attained by integrating a constant current (with high output impedance) over a capacitor, generating a linear ramp. The VTC operates at 256 MSPS consuming 1.3 mW from 1 V supply with a full-scale 1 V pk-pk differential input signal, while achieving a time-domain output signal with a spurious-free-dynamic-range (SFDR) of 77 dB and a signal-to-noise-and-distortion ratio (SNDR) of 56 dB at close to Nyquist frequency (f = 126.5 MHz). The proposed VTC attains an output range of 2.7 ns, which is the highest linear output range for a VTC at this speed, published to date

Design of a Comparator and an Amplifier in CMOS using standard logic gates

Using standard logic gates in CMOS, or standard-cells, has the advantage of full synthe- sizability, as well as the voltage scalability between technologies. In this work a general pur- pose standard-cell-based voltage comparator and amplifier are presented. The objective is to design a general purpose standard-cell-based comparator and ampli- fier in 130 nm CMOS by optimizing the already existing topologies with the aim of improving some of the specifications of the studied topologies. Various simulation testbenches were made to test the studied topologies of comparators and amplifiers, in which the results were compared. The top performing standard-cell com- parator and amplifier were then modified. After successfully designing the comparator, it was used in the design of an opamp-less Sigma-Delta modulator (ΣΔM). The proposed comparator is an OR-AND-Inverter-based comparator with dual inputs and outputs, achieving a delay of 109 ps, static input offset of 591 μV, and random offset of 10.42 μV, while dissipating 890 μW, when clocked at 1.5 GHz. The proposed amplifier is a single-path three-stage inverter-based operational transcon- ductance amplifier (OTA) with active common-mode feedback loop, achieving a DC gain of 63 dB, 1444 MHz of unity-gain bandwidth, 51º of phase margin while dissipating 1098 μW, considering a load of 1 pF. The proposed comparator was employed in the ΣΔM with a standard-cell based edge- triggered flip-flop. The ΣΔM, with a sampling frequency of 2 MHz and a signal bandwidth of 2.5 kHz, achieved a peak SNDR of 69 dB while dissipating only 136.7 μW.Utilizando portas lógicas básicas em CMOS oferece a vantagem de um circuito comple- tamente sintetizável, tal como o escalamento de tensão entre tecnologias. Neste trabalho são apresentados um comparador de tensão e um amplificador utilizando portas lógicas. O objetivo deste trabalho é desenhar um comparador e um amplificador utilizando por- tas lógicas através do estudo e otimização de topologias já existentes com a finalidade de me- lhoramento de algumas das especificações das mesmas. Foram realizados vários bancos de teste para testar as topologias estudadas de compa- radores e amplificadores, em que os resultados foram comparados. As topologias de compa- radores e amplificadores de portas lógicas com melhor performance foram então modificadas. Após o comparador ter sido projetado com sucesso, foi utilizado na projeção de um modula- dor Sigma-Delta (ΣΔM) opamp-less. O comparador proposto é um OR-AND-Inversor com duas entradas e saídas, que apre- senta um atraso de 109 ps, offset estático na entrada de 591 μV, offset aleatório de 10.42 μV, enquanto dissipando 890 μW, utilizando uma frequência de relógio de 1.5 GHz O amplificador proposto é um amplificador operacional de transcondutância single- path three-stage inverter-based com um loop ativo de realimentação do modo-comum, que apresenta um ganho DC de 63 dB, 1444 MHz de ganho-unitário de largura de banda, 51º de margem de fase e dissipando 1098 μW, considerando uma carga de 1 pF. O comparador proposto foi aplicado no ΣΔM com um flip-flop edge-triggered baseado em portas lógicas. O ΣΔM, com uma frequência de amostragem de 2 MHz e uma largura de banda de 2.5 kHz, apresentou um SNDR máximo de 69 dB enquanto dissipando apenas 136.7 μW

Design and Analysis of a Low-Power 8-Bit 500 KS/S SAR ADC for Bio-Medical Implant Devices

This thesis project involves the design and analysis of an 8-bit Successive Approximation Register (SAR) Analog to Digital Convertor (ADC), designed for low- power applications such as bio-medical implants. The sampling rate for this ADC is 500 KS/s. The power consumption for the whole SAR ADC system was measured to be 2.1 uW. The novelty of this project is the proposal of an extremely energy efficient comparator architecture. The result is the design of a final ADC with reasonable sampling speed, accuracy and low power consumption. In this project, all the different subsystems have been designed at the transistor level with 45 nm CMOS technology. The logical circuit was designed using Verilog language. It was then synthesized and integrated in the overall system

All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications

SMART-E-PTDC/CTM-PAM/04012/2022, IDS-PAPER-PTDC/CTM-PAM/4241/2020 and PEST (CTS/UNINOVA)-UIDB/00066/2020. This work also received funding from the European Community’s H2020 program [Grant Agreement No. 716510 (ERC-2016-StG TREND) and 952169 (SYNERGY, H2020-WIDESPREAD-2020-5, CSA)]. Publisher Copyright: © 2022 by the authors.In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-ΔM with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated (Formula presented.) is close to 16.2 fJ/conv.-step.publishersversionpublishe

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Low-power high-speed ADC design techniques in scaled CMOS process

The power consumption of a single-channel successive approximation register (SAR) analog-to-digital (ADC) tends to linearly increase with its sampling rate (f[subscript s]), when f[subscript s] is small. However, when f[subscript s] passes a certain point for a given technology node, the ADC power P increases at much higher rate and the normalized power efficiency (P/f[subscript s]) starts to degrade rapidly. To enhance the conversion speed of SAR ADC, while maintaining a good power efficiency, this thesis presents speed-enhancing techniques for SAR ADC in nano-scale CMOS technologies. First chapter presents a 2b/cycle hybrid SAR architecture with only 1 differential capacitor-DAC (CDAC). Unlike prior multi-bit/cycle SAR works that make use of only the DAC differential mode (DM) voltage, the proposed architecture exploits both the DM and the common mode (CM). By using two degrees of freedom, 2b/cycle conversion technique can boost the f[subscript s] of the ADC without any additional DAC arrays. High-speed ADCs can boost the conversion speed not only by increasing the f[subscript s] of a single-channel ADC, but also by time-interleaving multiple ADC sub-channels running at a lower rate. For an N-channel time-interleaved (TI) SAR ADC operating at f[subscript s], each sub-SAR channel only needs to operate at f[subscript s]=N. Therefore, each sub-SAR can operate in the linear power versus speed region, leading to a significant power saving compared to a single-channel ADC running at the same sampling rate. Despite of its power efficiency, TI-ADC suffers from mismatches among sub-ADC channels, including gain, offset, and timing mismatches. Among them, timing skew is one of the most difficult errors to calibrate as it is nontrivial to extract and its induced error depends on both the frequency and the amplitude of the input signal. Second chapter of this thesis presents a TI-SAR with a fast variance-based timing-skew calibration technique. It uses a single-comparator based window detector (WD) to calibrate the timing skew. The WD suppresses variance estimation errors and allow precise variance estimation from a significantly small number of samples. It has low-hardware cost and orders of magnitude faster convergence speed compared to prior variance-based timing-skew calibration technique. The last chapter presents another TI-SAR with mean absolute deviation (MAD) based timing-skew calibration technique. In addition to all the advantages presented with the fast variance-based timing-skew calibration technique, the proposed technique further reduces the digital computation power by 50% by eliminating the squaring operations, which are essential in variance-based calibration techniqueElectrical and Computer Engineerin

Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology

Low-power, medium resolution, high-speed analog-to-digital converters (ADCs) have always been important block which have abundant applications such as digital signal processors (DSP), imaging sensors, environmental and biomedical monitoring devices. This study presents a low power Flash ADC designed in nanometer complementary metal-oxide semiconductors (CMOS) technology. Time analysis on the output delay of the comparators helps to generate one more bit. The proposed technique reduced the power consumption and chip area substantially in comparison to the previous state-of-the-art work. The proposed ADC was developed in TSMC 65nm CMOS technology. The offset cancellation technique was embedded in the proposed comparator to decrement the static offset of the comparator. Moreover, one more bit was generated without using extra comparators. The proposed ADC achieved 4.1 bits ENOB at input Nyquist frequency. The simulated differential and integral non-linearity static tests were equal to +0.26/-0.17 and +0.22/-0.15, respectively. The ADC consumed 7.7 mW at 1 GHz sampling frequency, achieving 415 fJ/Convstep Figure of Merit (FoM)

REALIZATION OF A VARIABLE RESOLUTION MODIFIED SEMIFLASH ADC BASED ON BIT SEGMENTATION SCHEME

A modified variable resolution semiflash ADC, based on ‘bit segmentation scheme’, is presented. Its speed and comparator count are identical to a normal flash ADC. An 8-bit ADC has 256 different bit combinations. Sixteen consecutive bit combinations from the MSB side – beginning with the first one, remain unaltered for such an ADC. It continues this way till the last group of sixteen bits. In the designed circuit, the four MSB and four LSB bits are determined in the first and second part of the clock. Following the same logic, the bits in a 16-bit ADC can be found out in only two clock cycles by employing only fifteen comparators. It implies that a higher resolution ADC can easily be determined with low power and small die area. It is tested in P-SIM Professional 9 for an 8-bit ADC and curves drawn to establish the validity of the proposal

Energy Efficient Pipeline ADCs Using Ring Amplifiers

Pipeline ADCs require accurate amplification. Traditionally, an operational transconductance amplifier (OTA) configured as a switched-capacitor (SC) amplifier performs such amplification. However, traditional OTAs limit the power efficiency of ADCs since they require high quiescent current for slewing and bandwidth. In addition, it is difficult to design low-voltage OTAs in modern, scaled CMOS. The ring amplifier is an energy efficient and high output swing alternative to an OTA for SC circuits which is basically a three-stage inverter amplifier stabilized in a feedback configuration. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. In this dissertation, three types of innovative ring amplifiers are presented and verified with state-of-the-art energy efficient pipeline ADCs. These new ring amplifiers overcome the limitations of the conventional ring amplifier and further improve energy efficiency. The first topic of this dissertation is a self-biased ring amplifier that makes the ring amplifier more practical and power efficient, while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. In addition, the ring amplifiers are also used as comparators in the 1.5b sub-ADCs by utilizing the unique characteristics of the ring amplifier. This removes the need for dedicated comparators in sub-ADCs, thus further reducing the power consumption of the ADC. The prototype 10.5b 100 MS/s comparator-less pipeline ADC with the self-biased ring amplifiers has measured SNDR, SNR and SFDR of 56.6 dB (9.11b), 57.5 dB and 64.7 dB, respectively, and consumes 2.46 mW, which results in Walden Figure-of-Merit (FoM) of 46.1 fJ/ conversion∙step. The second topic is a fully-differential ring amplifier, which solves the problems of single-ended ring amplifiers while maintaining the benefits of the single-ended ring amplifiers. This differential ring-amplifier is applied in a 13b 50 MS/s SAR-assisted pipeline ADC. Furthermore, an improved capacitive DAC switching method for the first stage SAR reduces the DAC linearity errors and switching energy. The prototype ADC achieves measured SNDR, SNR and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, and consumes 1 mW. This measured performance is equivalent to Walden and Schreier FoMs of 6.9 fJ/conversion∙step and 174.9 dB, respectively. Finally, a four-stage fully-differential ring amplifier improves the small-signal gain to over 90 dB without compromising speed. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. This is more area efficient than the conventional auto-zero noise folding reduction technique. A systematic mismatch free SAR CDAC layout method is also presented. The prototype 15b 100 MS/s calibration-free SAR-assisted pipeline ADC using the four-stage ring amplifier achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in Schreier FoM of 176.6 dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138759/1/yonglim_1.pd

Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance