An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

DESIGN AND CHARACTERIZATION OF LOW-POWER LOW-NOISE ALLDIGITAL SERIAL LINK FOR POINT-TO-POINT COMMUNICATION IN SOC

The fully-digital implementation of serial links has recently emerged as a viable alternative to their classical analogue counterpart. Indeed, reducing the analogue content in favour of expanding the digital content becomes more attractive due to the ability to achieve less power consumption, less sensitivity to the noise and better scalability across multiple technologies and platforms with inconsiderable modifications. In addition, describing the circuit in hardware description languages gives it a high flexibility to program all design parameters in a very short time compared with the analogue designs which need to be re-designed at transistor level for any parameter change. This can radically reduce cost and time-to-market by saving a significant amount of development time. However, beside these considerable advantages, the fully-digital architecture poses several design challenges

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion

A Bang-Bang All-Digital PLL for Frequency Synthesis

abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time.Dissertation/ThesisM.S. Electrical Engineering 201

A low power signal front-end for passive UHF RFID transponders with a new clock recovery circuit.

Chan, Chi Fat.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.Includes bibliographical references.Abstracts in English and Chinese.Abstract --- p.2摘要 --- p.5Acknowledgement --- p.7Table of Contents --- p.9List of Figures --- p.11List of Tables --- p.14Chapter 1. --- Introduction --- p.15Chapter 1.2. --- Research Objectives --- p.16Chapter 1.3. --- Thesis Organization --- p.18Chapter 1.4. --- References --- p.19Chapter 2. --- Overview of Passive UHF RFID Transponders --- p.20Chapter 2.1. --- Types of RFID Transponders and Design Challenges of Passive RFID Transponder --- p.20Chapter 2.2. --- Selection of Carrier Frequency --- p.22Chapter 2.3. --- Description of Transponder Construction --- p.22Chapter 2.3.1. --- Power-Generating Circuits --- p.23Chapter 2.3.2. --- Base Band Processor --- p.28Chapter 2.3.3. --- Signal Front-End --- p.29Chapter 2.4. --- Summary --- p.30Chapter 2.5. --- References --- p.31Chapter 3. --- ASK Demodulator for EPC C-l G-2 Transponder --- p.32Chapter 3.1. --- ASK Demodulator Design Considerations --- p.32Chapter 3.1.1. --- Recovered Envelope Distortion --- p.32Chapter 3.1.2. --- Input Power Level Considerations --- p.34Chapter 3.1.3. --- Input RF power Intercepted by ASK Demodulator --- p.36Chapter 3.2. --- ASK Demodulator Design From [3-4] --- p.36Chapter 3.2.1. --- Envelope Waveform Recovery Design --- p.37Chapter 3.2.1.1. --- Voltage Multiplier Branch for Generating Venv --- p.39Chapter 3.2.1.2. --- Voltage Multiplier Branch for Generating Vref --- p.41Chapter 3.2.2. --- Design Considerations for Sensitivity of ASK Demodulator --- p.41Chapter 3.2.3. --- RF Input Power Sharing with Voltage Multiplier --- p.44Chapter 3.2.4. --- ASK Demodulator and Voltage Multiplier Integrated Estimations for Maximum RF Power Input --- p.47Chapter 3.2.5. --- Measurement result and Discussion --- p.49Chapter 3.3. --- Proposed Envelope Detector Circuit --- p.52Chapter 3.3.1. --- Sensitivity Estimation --- p.52Chapter 3.3.2. --- Maximum Tolerable Input Power Estimation --- p.53Chapter 3.3.3. --- Envelope Waveform Recovery of the Proposed Envelope Detector --- p.54Chapter 3.4. --- Summary --- p.57Chapter 3.5. --- References --- p.58Chapter 4. --- Clock Generator for EPC C-l G-2 Transponder --- p.59Chapter 4.1. --- Design Challenges Overview of Clock Generator --- p.59Chapter 4.2. --- Brief Review of PIE Symbols in EPC C1G2 Standard --- p.62Chapter 4.3. --- Proposed Clock Recovery Circuit Based on PIE Symbols for Clock Frequency Calibration --- p.64Chapter 4.3.1. --- Illustration on PIE Symbols for Clock Frequency Calibration --- p.64Chapter 4.3.2. --- Symbol time-length counter --- p.72Chapter 4.3.3. --- The M2.56MHZ Reference Generator and Sampling Frequency Requirement --- p.75Chapter 4.3.4. --- Symbol Length Reconfiguration for Different Tari and FLL Stability --- p.80Chapter 4.3.5. --- Frequency Detector and Loop Filter --- p.83Chapter 4.3.6. --- Proposed DCO Design --- p.84Chapter 4.3.7. --- Measurement Results and Discussions --- p.88Chapter 4.3.7.1. --- Frequency Calibration Measurement Results --- p.89Chapter 4.3.7.2. --- Number x and Tari Variation --- p.92Chapter 4.3.7.3. --- Temperature and Supply Variation --- p.93Chapter 4.3.7.4. --- Transient Supply Variation --- p.94Chapter 4.3.8. --- Works Comparison --- p.95Chapter 4.4. --- Clock Generator with Embedded PIE Decoder --- p.96Chapter 4.4.1. --- Clock Generator for Transponder Review --- p.96Chapter 4.4.2. --- PIE Decoder Review --- p.97Chapter 4.4.3. --- Proposed Clock Generator with Embedded PIE Decoder --- p.97Chapter 4.4.4. --- Measurement Results and Discussions --- p.100Chapter 4.5. --- Summary --- p.103Chapter 4.6. --- References --- p.105Chapter 5. --- ASK Modulator --- p.107Chapter 5.1. --- Introduction to ASK Modulator in RFD Transponder --- p.107Chapter 5.2. --- ASK Modulator Design --- p.109Chapter 5.3. --- ASK Modulator Measurement --- p.110Chapter 5.4. --- Summary --- p.113Chapter 5.5. --- References --- p.113Chapter 6. --- Conclusions --- p.114Chapter 6.1. --- Contribution --- p.114Chapter 6.2. --- Future Development --- p.11

High Performance Local Oscillator Design for Next Generation Wireless Communication

Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances. The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication. The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges. To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen- eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation. To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept. In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes. Finally, Chapter 6 presents the conclusion of this thesis

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Near-sensor data analytics is a promising direction for IoT endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data is stored or sent over the network at various stages of the analytics pipeline. Using encryption to protect sensitive data at the boundary of the on-chip analytics engine is a way to address data security issues. To cope with the combined workload of analytics and encryption in a tight power envelope, we propose Fulmine, a System-on-Chip based on a tightly-coupled multi-core cluster augmented with specialized blocks for compute-intensive data processing and encryption functions, supporting software programmability for regular computing tasks. The Fulmine SoC, fabricated in 65nm technology, consumes less than 20mW on average at 0.8V achieving an efficiency of up to 70pJ/B in encryption, 50pJ/px in convolution, or up to 25MIPS/mW in software. As a strong argument for real-life flexible application of our platform, we show experimental results for three secure analytics use cases: secure autonomous aerial surveillance with a state-of-the-art deep CNN consuming 3.16pJ per equivalent RISC op; local CNN-based face detection with secured remote recognition in 5.74pJ/op; and seizure detection with encrypted data collection from EEG within 12.7pJ/op.Comment: 15 pages, 12 figures, accepted for publication to the IEEE Transactions on Circuits and Systems - I: Regular Paper

IF-level signal-processing of GPS and Galileo Radionavigation signals using MATLAB/Simulink®: Including Effects of Interference and Multipath

Open-source GNSS simulator models are rare and somewhat difficult to find. Therefore, Laboratory of Electronics and Communications Engineering in the former Tampere University of Technology (and now Tampere University, Hervanta Campus) has took it upon itself to develop, from time to time, a free and open-source simulator model based on MATLAB/Simulink® for signal processing of a carefully selected set of GNSS radionavigation signals, namely, Galileo E1, Galileo E5, GPS L1, and GPS L5. This M.Sc. thesis is the culmination of those years which have been spent intermittently on research and development of that simulator model. The first half of this M.Sc. thesis is a literature review of some topics which are believed to be of relevance to the thesis’s second half which is in turn more closely associated with documenting the simulator model in question. In particular, the literature review part presents the reader with a plethora of GNSS topics ranging from history of GNSS technology to characteristics of existing radionavigation signals and, last but not least, compatibility and interoperability issues among existing GNSS constellations. While referring to the GNSS theory whenever necessary, the second half is, however, mainly focused on describing the inner-workings of the simulator model from the standpoint of software implementations. Finally, the second half, and thereby the thesis, is concluded with a presentation of various statistical results concerning signal acquisition’s probabilities of detection and false-alarm, in addition to signal tracking’s RMSE

The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology

The open-source RISC-V instruction set architecture (ISA) is gaining traction, both in industry and academia. The ISA is designed to scale from microcontrollers to server-class processors. Furthermore, openness promotes the availability of various open-source and commercial implementations. Our main contribution in this paper is a thorough power, performance, and efficiency analysis of the RISC-V ISA targeting baseline "application class" functionality, i.e., supporting the Linux OS and its application environment based on our open-source single-issue in-order implementation of the 64-bit ISA variant (RV64GC) called Ariane. Our analysis is based on a detailed power and efficiency analysis of the RISC-V ISA extracted from silicon measurements and calibrated simulation of an Ariane instance (RV64IMC) taped-out in GlobalFoundries 22FDX technology. Ariane runs at up to 1.7-GHz, achieves up to 40-Gop/sW energy efficiency, which is superior to similar cores presented in the literature. We provide insight into the interplay between functionality required for the application-class execution (e.g., virtual memory, caches, and multiple modes of privileged operation) and energy cost. We also compare Ariane with RISCY, a simpler and a slower microcontroller-class core. Our analysis confirms that supporting application-class execution implies a nonnegligible energy-efficiency loss and that compute performance is more cost-effectively boosted by instruction extensions (e.g., packed SIMD) rather than the high-frequency operation

Design of energy-efficient high-speed wireline transceiver

Energy efficiency has become the most important performance metric of integrated circuits used in many applications ranging from mobile devices to high-performance processors. The power problem permeates both computing and communication systems alike. Especially in the era of Big Data, continuously growing demand for higher communication bandwidth is driving the need for energy-efficient high-speed I/O serial links. However, the rate at which the energy efficiency of serial links is improving is much slower than the rate at which the required data transfer bandwidth is increasing. This dissertation explores two design approaches for energy-efficient communication systems. The first design approach maximizes the energy efficiency of a transceiver without any performance loss, and as a prototype, a source-synchronous multi-Gb/s transceiver that achieves excellent energy efficiency lower than 0.3pJ/bit is presented. To this end, the proposed transceiver employs aggressive supply voltage scaling, and multiplexed transmitter and receiver synchronized by low-rate multi-phase clocks are adopted to achieve high data rate even at a supply voltage close to the device threshold voltage. Phase spacing errors resulting from device mismatches are corrected using a self-calibration scheme. The proposed phase calibration method uses a single digital delay-locked loop (DLL) for calibrating all the phases, which makes the calibration process insensitive to the supply voltage level. Thanks to this technique, the proposed multi-Gb/s transceiver operates robustly and energy-efficiently at a very low supply voltage. Fabricated in a 65nm CMOS process, the energy efficiency and data rate of the prototype transceiver vary from 0.29pJ/bit to 0.58pJ/bit and 1Gb/s to 6Gb/s, respectively, as the supply voltage is varied from 0.45V to 0.7V. In the second approach, observing that the data traffic in a real system is bursty, a full-rate burst-mode transceiver that achieves rapid on/off operation needed for energy-proportional systems is presented. By injecting input data edges into the oscillator embedded in a classical type-II digital clock and data recovery (CDR) circuit, the proposed receiver achieves instantaneous phase-locking and input jitter filtering simultaneously. In other words, the proposed CDR combines the advantages of conventional feed-forward and feedback architectures to achieve energy-proportional operation. By controlling the number of data edges injected into the oscillator, both the jitter transfer bandwidth and the jitter tolerance corner are accurately controlled. The feedback loop also corrects for any frequency error and helps improve the CDR's immunity to oscillator frequency drift during the power-on and -off states. This also improves the CDR's tolerance to consecutive identical digits present in the input data. Fabricated in a 90nm CMOS process, the prototype receiver instantaneously locks onto the very first data edge and consumes 6.1mW at 2.2Gb/s. Owing to its short power-on time, the overall transceiver's energy efficiency varies only from 5.4pJ/bit to 10.7pJ/bit when the effective data rate is varied from 2.2Gb/s to 0.22Gb/s