Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude

Power efficient analog-to-digital converters using both voltage and time domain information

As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain quantizer by processing the signal in time rather than only in voltage domain especially for power efficiency. This research focuses on developing a new architecture for power efficient, high resolution ADCs using both voltage and time domain information. As a first approach, a new ΔƩ ADC based on a noise-shaped two-step integrating quantizer which quantizes the signal in voltage and time domains is presented. Attaining an extra order of noise-shaping from the integrating quantizer, the proposed ΔƩ ADC manifests a second-order noise-shaping with a first-order loop filter. Furthermore, this quantizer provides an 8b uantization in itself, drastically reducing the oversampling requirement. The proposed ADC also incorporates a new feedback DAC topology that alleviates the feedback DAC complexity of a two-step 8b quantizer. The measured results of the prototype ADC implemented in a 0.13μm CMOS demonstrate peak SNDR of 70.7dB (11.5b ENOB) at 8.1mW power, with an 8x OSR at 80MHz sampling frequency. To further improve ADC performance, a Nyquist ADC based on a time-based pipelined TDC is also proposed as a second approach. In this work, a simple V-T conversion scheme with a cheap low gain amplifier in its first stage and a hybrid time-domain quantization stage based on simple charge pump and capacitive DAC in its backend stages, are also proposed to improve ADC linearity and power efficiency. Using voltage and time domain information, the proposed ADC architecture is beneficial for both resolution and power efficiency, with MSBs resolved in voltage domain and LSBs in time domain. The measured results of the prototype ADC implemented in a 0.13μm CMOS demonstrate peak SNDR of 69.3dB (11.2b ENOB) at 6.38mW power and 70MHz sampling frequency. The FOM is 38.2fJ/conversion-step

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

An 8 Bit, 100ms/s Pipeline ADC with Partial Positive Feedback Amplifier for Cognitive Radio Applications

This thesis focuses on designing a low power Pipeline Analog to Digital Converter (ADC) for use in a Cognitive radio network. The Pipeline ADC architecture is one of the most suitable ADC architectures for applications requiring moderate to high operating speeds and resolution while consuming low power. The designed ADC introduces a Partial Positive Feedback amplifier which yields high gain with minimal power consumption without a need for a common mode feedback. A multiplexer–based Multiplying Digital to Analog Converter (MDAC) is also introduced. The multiplexer–based MDAC mitigates the capacitor mismatch effect encountered in the conventional MDAC. Clocked bootstrapped switches are designed to maintain constant on-resistance desired in switches. With a power supply of 2.4V, the Pipeline ADC consumed a total power of 8.2mW and achieved a Signal-to-Noise-and-Distortion Ratio (SNDR) of 48.08 dB which corresponds to an Effective Number of Bits (ENOB) of 7.69 bits at the Nyquist frequency. A Differential Non-Linearity error (DNL) of less than ±1 LSB ensuring that all codes corresponding to an 8 bit ADC are available. The Partial Positive Feedback amplifier used achieved an open loop gain of 51 dB while consuming 1.8mA of current. The designed Pipeline ADC achieved a Figure of Merit (FoM) of 0.38 pJ/conversion step

Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

Design Techniques for High-Performance SAR A/D Converters

The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology

Energy-efficient analog-to-digital conversion for ultra-wideband radio

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 207-222).In energy constrained signal processing and communication systems, a focus on the analog or digital circuits in isolation cannot achieve the minimum power consumption. Furthermore, in advanced technologies with significant variation, yield is traditionally achieved only through conservative design and a sacrifice of energy efficiency. In this thesis, these limitations are addressed with both a comprehensive mixed-signal design methodology and new circuits and architectures, as presented in the context of an analog-to-digital converter (ADC) for ultra-wideband (UWB) radio. UWB is an emerging technology capable of high-data-rate wireless communication and precise locationing, and it requires high-speed (>500MS/s), low-resolution ADCs. The successive approximation register (SAR) topology exhibits significantly reduced complexity compared to the traditional flash architecture. Three time-interleaved SAR ADCs have been implemented. At the mixed-signal optimum energy point, parallelism and reduced voltage supplies provide more than 3x energy savings. Custom control logic, a new capacitive DAC, and a hierarchical sampling network enable the high-speed operation. Finally, only a small amount of redundancy, with negligible power penalty, dramatically improves the yield of the highly parallel ADC in deep sub-micron CMOS.by Brian P. Ginsburg.Ph.D

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Design of Power Management Integrated Circuits and High-Performance ADCs

A battery-powered system has widely expanded its applications to implantable medical devices (IMDs) and portable electronic devices. Since portable devices or IMDs operate in the energy-constrained environment, their low-power operations in combination with efficiently sourcing energy to them are key problems to extend device life. This research proposes novel circuit techniques for two essential functions of a power receiving unit (PRU) in the energy-constrained environment, which are power management and signal processing. The first part of this dissertation discusses power management integrated circuits for a PRU. From a power management perspective, the most critical two circuit blocks are a front-end rectifier and a battery charger. The front-end CMOS active rectifier converts transmitted AC power into DC power. High power conversion efficiency (PCE) is required to reduce power loss during the power transfer, and high voltage conversion ratio (VCR) is required for the rectifier to enable low-voltage operations. The proposed 13.56-MHz CMOS active rectifier presents low-power circuit techniques for comparators and controllers to reduce increasing power loss of an active diode with offset/delay calibration. It is implemented with 5-V devices of a 0.35 µm CMOS process to support high voltage. A peak PCE of 89.0%, a peak VCR of 90.1%, and a maximum output power of 126.7 mW are measured for 200Ω loading. The linear battery charger stores the converted DC power into a battery. Since even small power saving can be enough to run the low-power PRU, a battery charger with low IvQ is desirable. The presented battery charger is based on a single amplifier for regulation and the charging phase transition from the constant-current (CC) phase to the constant-voltage (CV) phase. The proposed unified amplifier is based on stacked differential pairs which share the bias current. Its current-steering property removes multiple amplifiers for regulation and the CC-CV transition, and achieves high unity-gain loop bandwidth for fast regulation. The charger with the maximum charging current of 25 mA is implemented in 0.35 µm CMOS. A peak charger efficiency of 94% and average charger efficiency of 88% are achieved with an 80-mAh Li-ion polymer battery. The second part of this dissertation focuses on analog-to-digital converters (ADCs). From a signal processing perspective, an ADC is one of the most important circuit blocks in the PRU. Hence, an energy-efficient ADC is essential in the energy-constrained environment. A pipelined successive approximation register (SAR) ADC has good energy efficiency in a design space of moderate-to-high speeds and resolutions. Process-Voltage-Temperature variations of a dynamic amplifier in the pipelined-SAR ADC is a key design issue. This research presents two dynamic amplifier architectures for temperature compensation. One is based on a voltage-to-time converter (VTC) and a time-to-voltage converter (TVC), and the other is based on a temperature-dependent common-mode detector. The former amplifier is adopted in a 13-bit 10-50 MS/s subranging pipelined-SAR ADC fabricated in 0.13-µm CMOS. The ADC can operate under the power supply voltage of 0.8-1.2 V. Figure-of-Merits (FoMs) of 4-11.3 fJ/conversion-step are achieved. The latter amplifier is also implemented in 0.13-µm CMOS, consuming 0.11 mW at 50 MS/s. Its measured gain variation is 2.1% across the temperature range of -20°C to 85 °C