Arithmetic Operations in Multi-Valued Logic

This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.Comment: 12 Pages, VLSICS Journal 201

Design of High Performance Quaternary Adders

Design of the binary logic circuits is limited by the requirement of the interconnections. A possible solution could be arrived at by using a larger set of signals over the same chip area. Multiple-valued logic (MVL) designs are gaining importance from that perspective. This paper presents two types of multiple-valued full adder circuits, implemented in Multiple-Valued voltage-Mode Logic (MV-VML). First type is designed using one hot encoding and barrel shifter. Second full adder circuit is designed by converting the quaternary logic in to unique code, which enables to implement circuit with reduced hard ware. Sum and carry are processed in two separate blocks, controlled by code generator unit. The design is targeted for the 0.18 μm CMOS technology and verification of the design is done through Synopsis HSPICE and COSMOSCOPE Tools. Area of the designed circuits is less than the corresponding binary circuits and quaternary adders because number of transistors used are less

Design of 16-Bit Quaternary adder using Various Encoding Techniques

Design of binary circuit is restricted by the necessity of the interconnection. A conceivable arrangement could be touched base at by utilizing a bigger arrangement of signs over the same chip region. Quaternary outlines are picking up significance from that point of view. In this paper we design two types of full adder based on quaternary logic is proposed which will reduced the parameter such as area, power, and delay. The feature of this full adder is based on one hot encoding technique and binary encoding technique. All the design is using 180nm CMOS techniques. Sum and carry blocks are handled in two separate square controlled by the code generator unit. Plan check will be done by tanner tools

Validation of Octanary Adders in VHDL

Adders being the lowest building block in circuits, if can handle more data then certainly it can lead to smaller Silicon Area, low power consumption & Higher speed which can help in increasing portability in devices. Binary Logic Circuit design is limited by the number of bits that can be handled and interconnections. Multi Valued logic gives an extra dimension and thus extends the binary logic where more than two values can be dealt with. This paper gives the concept of octanary adders, and its simulation on Xilinx ISE Design Studio 13.

ハードウェアリソースの高稼働率化に基づく細粒度多値リコンフィギャラブルVLSIアーキテクチャ

Tohoku University亀山充隆課

Design of multi-valued quaternary based analog-to-digital converter

Problem statement: The design of multi-valued quaternary based Analog-to-Digital Converter (ADC) circuit was presented. The ADC generates multi-valued logic outputs rather than the conventional binary output system to overall reduction in circuit complexity and size. Approach: Design was implemented using pipeline ADC architecture and was simulated using model parameters based on standard 0.13 µm CMOS process. Results: Performance analysis of the design showed desirable performance parameters in terms of response, low power consumption, and a sampling rate of 10 MHz at a supply voltage of 1.3V was achieved. Conclusion/Recommendations: The ADC design was suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple-valued logic design

The implementation and applications of multiple-valued logic

Multiple-Valued Logic (MVL) takes two major forms. Multiple-valued circuits can implement the logic directly by using multiple-valued signals, or the logic can be implemented indirectly with binary circuits, by using more than one binary signal to represent a single multiple-valued signal. Techniques such as carry-save addition can be viewed as indirectly implemented MVL. Both direct and indirect techniques have been shown in the past to provide advantages over conventional arithmetic and logic techniques in algorithms required widely in computing for applications such as image and signal processing. It is possible to implement basic MVL building blocks at the transistor level. However, these circuits are difficult to design due to their non binary nature. In the design stage they are more like analogue circuits than binary circuits. Current integrated circuit technologies are biased towards binary circuitry. However, in spite of this, there is potential for power and area savings from MVL circuits, especially in technologies such as BiCMOS. This thesis shows that the use of voltage mode MVL will, in general not provide bandwidth increases on circuit buses because the buses become slower as the number of signal levels increases. Current mode MVL circuits however do have potential to reduce power and area requirements of arithmetic circuitry. The design of transistor level circuits is investigated in terms of a modern production technology. A novel methodology for the design of current mode MVL circuits is developed. The methodology is based upon the novel concept of the use of non-linear current encoding of signals, providing the opportunity for the efficient design of many previously unimplemented circuits in current mode MVL. This methodology is used to design a useful set of basic MVL building blocks, and fabrication results are reported. The creation of libraries of MVL circuits is also discussed. The CORDIC algorithm for two dimensional vector rotation is examined in detail as an example for indirect MVL implementation. The algorithm is extended to a set of three dimensional vector rotators using conventional arithmetic, redundant radix four arithmetic, and Taylor's series expansions. These algorithms can be used for two dimensional vector rotations in which no scale factor corrections are needed. The new algorithms are compared in terms of basic VLSI criteria against previously reported algorithms. A pipelined version of the redundant arithmetic algorithm is floorplanned and partially laid out to give indications of wiring overheads, and layout densities. An indirectly implemented MVL algorithm such as the CORDIC algorithm described in this thesis would clearly benefit from direct implementation in MVL

Modem design for digital satellite communications

The thesis is concerned with the design of a phase-shift keying system for a digital modem, operating over a satellite link. Computer simulation tests and theoretical analyses are used to assess the proposed design. The optimum design of both transmitter and receiver filters for the system to be used in the modem are discussed. Sinusoidal roll-off spectrum with different roll-off factor and optimum truncation lengths of the sample impulse response are designed for the proposed scheme to approximate to the theoretical ideal. It has used an EF bandpass filter to band limit the modulated signal, which forms part of the satellite channel modelling. The high power amplifier (HPA) at the earth station has been used in the satellite channel modelling due to its effect in introducing nonlinear AMAM and AM-PM conversion effects and distortion on the transmitted signal from the earth station. The satellite transponder is assumed to be operating in a linear mode. Different phase-shift keying signals such as differentially encoded quaternary phase-shift keying (DEQPSK), offset quaternary phase-shift keying (OQPSK) and convolutionally encoded 8PSK (CE8PSK) signals are analysed and discussed in the thesis, when the high power amplifier (HPA) at the earth station is operating in a nonlinear mode. Convolutional encoding is discussed when applied to the system used in the modem, and a Viterbi -algorithm decoder at the receiver has been used, for CE8PSK signals for a nonlinear satellite channel. A method of feed-forward synchronisation scheme is designed for carrier recovery in CE8PSK receiver. The thesis describes a method of baseband linearizing the baseband signal in order to reduce the nonlinear effects caused by the HPA at the earth station. The scheme which compensates for the nonlinear effects of the HPA by predistorting the baseband signal prior to modulation as opposed to correcting the distortion after modulation, thus reducing the effects of nonlinear distortion introduced by the HPA. The results of the improvement are presented. The advanced technology of digital signal processors (DSPs) has been used in the implementation of the demodulation and digital filtering parts of the modem replacing large parts of conventional circuits. The Viterbi-algorithm decoder for CE8PSK signals has been implemented using a digital signal processor chip, giving excellent performance and is a cost effective and easy way for future developments and any modifications, The results showed that, by using the various studied techniques, as well as the implementation of digital signal processor chip in parts of the modem, a potentially more cost effective modem can be obtained

暗号ハードウェアの形式的設計に関する研究

Tohoku University青木孝文課