63 research outputs found
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Stealthy parametric hardware Trojans in VLSI Circuits
Over the last decade, hardware Trojans have gained increasing attention in academia, industry and by government agencies. In order to design reliable countermeasures, it is crucial to understand how hardware Trojans can be built in practice. This is an area that has received relatively scant treatment in the literature. In this thesis, we examine how particularly stealthy parametric Trojans can be introduced to VLSI circuits. Parametric Trojans do not require any additional logic and are purely based on subtle manipulations on the sub-transistor level to modify the parameters of few transistors which makes them very hard to detect.
We introduce a design methodology to insert stealthy parametric hardware Trojans which are based on injecting extremely rare path delay faults into the netlist of the target circuit. As a case study, we apply our method to a 32-bit multiplier circuit resulting in a stealthy Trojan multiplier that computes faulty outputs for specific combinations of input pairs that are applied to the circuit. The multiplier can be used to realize bug attacks, introduced by Biham et al. in 2008. We also extend this concept and show how it can be used to attack ECDH key agreement protocols. Our method is a versatile tool for designing stealthy Trojans for a given circuit and is not restricted to multipliers and the bug attack.
In this thesis we also examine how a stealthy side-channel hardware Trojan can be inserted in a provably-secure side-channel analysis protected implementation. Once the Trojan is triggered, the malicious design exhibits exploitable side-channel leakage leading to successful key recovery attacks. The underlying concept is based on a secure masked hardware implementation which does not exhibit any detectable leakage. However, by running the device at a particular clock frequency one of the requirements of the underlying masking scheme is not fulfilled anymore, and the device\u27s side-channel leakage can be exploited. We apply our technique to a Threshold Implementation of the PRESENT block cipher realized in both FPGA and ASIC. We show that triggering the Trojan makes both FPGA and ASIC prototypes vulnerable to certain SCA attacks.
True random number generators (TRNGs) are an essential component of cryptographic designs, which are used to generate private keys for encryption and authentication, and are used in masking countermeasures. This thesis also presents a mechanism to design a stealthy parametric hardware Trojan for ring oscillator-based TRNGs. When the Trojan is triggered by operation at a specific high temperature the malicious TRNG generates predictable non-random outputs, yet under normal operating conditions it works correctly. Also we elaborate a stochastic model based on Markov Chains by which the attacker can use their knowledge of the Trojan to predict the TRNG outputs
D2.1 - Report on Selected TRNG and PUF Principles
This report represents the final version of Deliverable 2.1 of the HECTOR work package WP2. It is a result of discussions and work on Task 2.1 of all HECTOR partners involved in WP2. The aim of the Deliverable 2.1 is to select principles of random number generators (RNGs) and physical unclonable functions (PUFs) that fulfill strict technology, design and security criteria. For example, the selected RNGs must be suitable for implementation in logic devices according to the German AIS20/31 standard. Correspondingly, the selected PUFs must be suitable for applying similar security approach. A standard PUF evaluation approach does not exist, yet, but it should be proposed in the framework of the project. Selected RNGs and PUFs should be then thoroughly evaluated from the point of view of security and the most suitable principles should be implemented in logic devices, such as Field Programmable Logic Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) during the next phases of the project
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FPGA Security Techniques with Applications to Cloud and Multi-Tenant Use Cases
Field programmable gate arrays (FPGAs) are integrated circuits that consist of programmable logic that a user can configure and deploy for applications such as hardware emulation and accelerating high performance computing. In recent years, the emergence of FPGAs in the cloud has led to research on multi-tenant FPGAs. In a multi-tenant scenario, the same FPGA fabric is shared among multiple users, or among multiple untrusting IP cores. Multi-tenancy has economic benefits, largely due to improvements in resource utilization, but also brings new security concerns since the tenants could behave maliciously. Although the tenants sharing an FPGA are logically isolated from each other, they may still have unintended interactions through side channel attacks and fault attacks. In this dissertation, we aim to evaluate security threats and defenses in the multi-tenant FPGA scenario. Firstly, the work in this dissertation studies a true random number generator (TRNG) on cloud FPGAs that is robust against voltage manipulation from co-tenants. The TRNG design is based on harvesting clock jitter using a tunable time-to-digital converter circuit. In accordance with best practices, a stochastic model is built to evaluate the min-entropy of the design, and further validated by NIST entropy assessment test suite and NIST statistical tests. The basic version of the TRNG is extended with a linkable sampling module to increase min-entropy per sample and throughput at a modest resource cost. Then the dissertation analyzes a type of fault attack that can be conducted by one tenant against another in a multi-tenant setting. Specifically, the fault attack is differential fault intensity analysis (DFIA), which is a biased-fault based attack on Advanced Encryption Standard (AES) circuits. Ring oscillators (ROs) are deployed as effective power wasters to cause a supply voltage drop through the shared power distribution network (PDN) of tenants. The attack is highly relevant to multi-tenant scenarios because the attacking tenant can create the voltage drop without physical access, and can precisely control the shape of the voltage drop by adjusting both the number of activated ROs and their duration as required for the attack. The voltage drop will in turn increase the delay in the logic and eventually cause specific timing faults which are analyzed to successfully recover the AES keys. In the last part, we use on-chip voltage sensors to detect the location of a target circuits. The sensing scheme leverages time-to-digital converters (TDCs) as voltage sensors, and a novel differential analysis is applied to the sensor data. In a multi-tenant setting, this method can be used either as part of a defensive scheme to monitor against attacks, or it can be used to probe a system and determine how to effectively target an attack to a particular co-tenant victim
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A STANDARDS COMPLIANT ENTROPY SOURCE WITH A FAST ON-THE-FLY ENTROPY DEGRADATION DETECTION AND CORRECTION
Since the advent of technology and world digitalization, most human interaction relies on data exchange through cloud servers on the internet. However, with the innovation also arose concerns about users' privacy and vulnerability. Therefore, cryptography and authentication are essential to protect users' data so only the owner and trusted parties can access it. The security system is the module responsible for securing data inside the devices. The hardware root of trust dwells inside the security system module. True random number generators are the most crucial root of trust devices since they generate the encryption keys. A weak key gives an advantage to an intruder to quickly break the cryptography and steal the data. However, true random number generators are powered by entropy sources susceptible to voltage, temperature, and process variation, which degrades the key entropy. This work proposes an all-digital reconfigurable entropy source with a dual-mode digital processing unit for entropy degradation detection and correction. The processing unit is powered by a subset of statistical tests from the national institute of Standards and Technologies (NIST) and the German Federal Office for Information Security (BSI), which detect and recover the entropy source output entropy within 1.5ms, 15 to 525x faster than similar works. Measured results show that the application specific integrated circuit (ASIC) entropy source yields random bits at a throughput of 1Mb/s with a min-entropy of 0.993 bits at 0.8V. The design consumes up to 42.6ÎĽW and occupies an area of 2834ÎĽm2 (without the on-chip register bank). Moreover, both the ASIC and the field programable array (FPGA) implementations passed all the NIST and BSI certification testing procedures
A PUF based on transient effect ring oscillator and insensitive to locking phenomenon
International audienceThis paper presents a new silicon physical unclonable function (PUF) based on a transient effect ring oscillator (TERO). The proposed PUF has state of the art PUF characteristics with a good ratio of PUF response variability to response length. Unlike RO-PUF, it is not sensitive to the locking phenomenon, which challenges the use of ring oscillators for the design of both PUF and TRNG. The novel architecture using differential structures guarantees high stability of the TERO-PUF. The area of the TERO-PUF is relatively high, but is still comparable with other PUF designs. However, since the same piece of hardware can be used for both PUF and random number generation, the proposed principle offers an interesting low area mixed solution
Digital Design of New Chaotic Ciphers for Ethernet Traffic
Durante los Ăşltimos años, ha habido un gran desarrollo en el campo de la criptografĂa, y muchos algoritmos de encriptado asĂ como otras funciones criptográficas han sido propuestos.Sin embargo, a pesar de este desarrollo, hoy en dĂa todavĂa existe un gran interĂ©s en crear nuevas primitivas criptográficas o mejorar las ya existentes. Algunas de las razones son las siguientes:• Primero, debido el desarrollo de las tecnologĂas de la comunicaciĂłn, la cantidad de informaciĂłn que se transmite está constantemente incrementándose. En este contexto, existen numerosas aplicaciones que requieren encriptar una gran cantidad de datos en tiempo real o en un intervalo de tiempo muy reducido. Un ejemplo de ello puede ser el encriptado de videos de alta resoluciĂłn en tiempo real. Desafortunadamente, la mayorĂa de los algoritmos de encriptado usados hoy en dĂa no son capaces de encriptar una gran cantidad de datos a alta velocidad mientras mantienen altos estándares de seguridad.• Debido al gran aumento de la potencia de cálculo de los ordenadores, muchos algoritmos que tradicionalmente se consideraban seguros, actualmente pueden ser atacados por mĂ©todos de “fuerza bruta” en una cantidad de tiempo razonable. Por ejemplo, cuando el algoritmo de encriptado DES (Data Encryption Standard) fue lanzado por primera vez, el tamaño de la clave era sĂłlo de 56 bits mientras que, hoy en dĂa, el NIST (National Institute of Standards and Technology) recomienda que los algoritmos de encriptado simĂ©tricos tengan una clave de, al menos, 112 bits. Por otro lado, actualmente se está investigando y logrando avances significativos en el campo de la computaciĂłn cuántica y se espera que, en el futuro, se desarrollen ordenadores cuánticos a gran escala. De ser asĂ, se ha demostrado que algunos algoritmos que se usan actualmente como el RSA (Rivest Shamir Adleman) podrĂan ser atacados con Ă©xito.• Junto al desarrollo en el campo de la criptografĂa, tambiĂ©n ha habido un gran desarrollo en el campo del criptoanálisis. Por tanto, se están encontrando nuevas vulnerabilidades y proponiendo nuevos ataques constantemente. Por consiguiente, es necesario buscar nuevos algoritmos que sean robustos frente a todos los ataques conocidos para sustituir a los algoritmos en los que se han encontrado vulnerabilidades. En este aspecto, cabe destacar que algunos algoritmos como el RSA y ElGamal están basados en la suposiciĂłn de que algunos problemas como la factorizaciĂłn del producto de dos nĂşmeros primos o el cálculo de logaritmos discretos son difĂciles de resolver. Sin embargo, no se ha descartado que, en el futuro, se puedan desarrollar algoritmos que resuelvan estos problemas de manera rápida (en tiempo polinomial).• Idealmente, las claves usadas para encriptar los datos deberĂan ser generadas de manera aleatoria para ser completamente impredecibles. Dado que las secuencias generadas por generadores pseudoaleatorios, PRNGs (Pseudo Random Number Generators) son predecibles, son potencialmente vulnerables al criptoanálisis. Por tanto, las claves suelen ser generadas usando generadores de nĂşmeros aleatorios verdaderos, TRNGs (True Random Number Generators). Desafortunadamente, los TRNGs normalmente generan los bits a menor velocidad que los PRNGs y, además, las secuencias generadas suelen tener peores propiedades estadĂsticas, lo que hace necesario que pasen por una etapa de post-procesado. El usar un TRNG de baja calidad para generar claves, puede comprometer la seguridad de todo el sistema de encriptado, como ya ha ocurrido en algunas ocasiones. Por tanto, el diseño de nuevos TRNGs con buenas propiedades estadĂsticas es un tema de gran interĂ©s.En resumen, es claro que existen numerosas lĂneas de investigaciĂłn en el ámbito de la criptografĂa de gran importancia. Dado que el campo de la criptografĂa es muy amplio, esta tesis se ha centra en tres lĂneas de investigaciĂłn: el diseño de nuevos TRNGs, el diseño de nuevos cifradores de flujo caĂłticos rápidos y seguros y, finalmente, la implementaciĂłn de nuevos criptosistemas para comunicaciones Ăłpticas Gigabit Ethernet a velocidades de 1 Gbps y 10 Gbps. Dichos criptosistemas han estado basados en los algoritmos caĂłticos propuestos, pero se han adaptado para poder realizar el encriptado en la capa fĂsica, manteniendo el formato de la codificaciĂłn. De esta forma, se ha logrado que estos sistemas sean capaces no sĂłlo de encriptar los datos sino que, además, un atacante no pueda saber si se está produciendo una comunicaciĂłn o no. Los principales aspectos cubiertos en esta tesis son los siguientes:• Estudio del estado del arte, incluyendo los algoritmos de encriptado que se usan actualmente. En esta parte se analizan los principales problemas que presentan los algoritmos de encriptado standard actuales y quĂ© soluciones han sido propuestas. Este estudio es necesario para poder diseñar nuevos algoritmos que resuelvan estos problemas.• Propuesta de nuevos TRNGs adecuados para la generaciĂłn de claves. Se exploran dos diferentes posibilidades: el uso del ruido generado por un acelerĂłmetro MEMS (Microelectromechanical Systems) y el ruido generado por DNOs (Digital Nonlinear Oscillators). Ambos casos se analizan en detalle realizando varios análisis estadĂsticos a secuencias obtenidas a distintas frecuencias de muestreo. TambiĂ©n se propone y se implementa un algoritmo de post-procesado simple para mejorar la aleatoriedad de las secuencias generadas. Finalmente, se discute la posibilidad de usar estos TRNGs como generadores de claves. • Se proponen nuevos algoritmos de encriptado que son rápidos, seguros y que pueden implementarse usando una cantidad reducida de recursos. De entre todas las posibilidades, esta tesis se centra en los sistemas caĂłticos ya que, gracias a sus propiedades intrĂnsecas como la ergodicidad o su comportamiento similar al comportamiento aleatorio, pueden ser una buena alternativa a los sistemas de encriptado clásicos. Para superar los problemas que surgen cuando estos sistemas son digitalizados, se proponen y estudian diversas estrategias: usar un sistema de multi-encriptado, cambiar los parámetros de control de los sistemas caĂłticos y perturbar las Ăłrbitas caĂłticas.• Se implementan los algoritmos propuestos. Para ello, se usa una FPGA Virtex 7. Las distintas implementaciones son analizadas y comparadas, teniendo en cuenta diversos aspectos tales como el consumo de potencia, uso de área, velocidad de encriptado y nivel de seguridad obtenido. Uno de estos diseños, se elige para ser implementado en un ASIC (Application Specific Integrate Circuit) usando una tecnologĂa de 0,18 um. En cualquier caso, las soluciones propuestas pueden ser tambiĂ©n implementadas en otras plataformas y otras tecnologĂas.• Finalmente, los algoritmos propuestos se adaptan y aplican a comunicaciones Ăłpticas Gigabit Ethernet. En particular, se implementan criptosistemas que realizan el encriptado al nivel de la capa fĂsica para velocidades de 1 Gbps y 10 Gbps. Para realizar el encriptado en la capa fĂsica, los algoritmos propuestos en las secciones anteriores se adaptan para que preserven el formato de la codificaciĂłn, 8b/10b en el caso de 1 Gb Ethernet y 64b/10b en el caso de 10 Gb Ethernet. En ambos casos, los criptosistemas se implementan en una FPGA Virtex 7 y se diseña un set experimental, que incluye dos mĂłdulos SFP (Small Form-factor Pluggable) capaces de transmitir a una velocidad de hasta 10.3125 Gbps sobre una fibra multimodo de 850 nm. Con este set experimental, se comprueba que los sistemas de encriptado funcionan correctamente y de manera sĂncrona. Además, se comprueba que el encriptado es bueno (pasa todos los test de seguridad) y que el patrĂłn del tráfico de datos está oculto.<br /
Modélisation et caractérisation des fonctions non clonables physiquement
Physically Unclonable Functions, or PUFs, are innovative technologies devoted to solve some security and identification issues. Similarly to a human fingerprint, PUFs allows to identify uniquely electronic devices as they produce an instance-specific signature. Applications as authentication or key generation can take advantage of this embedded function. The main property that we try to obtain from a PUF is the generation of a unique response that varies randomly from one physical device to another without allowing its prediction. Another important property of these PUF is to always reproduce the same response for the same input challenge even in a changing environment. Moreover, the PUF system should be secure against attacks that could reveal its response. In this thesis, we are interested in silicon PUF which take advantage of inherent process variations during the manufacturing of CMOS integrated circuits. We present several PUF constructions, discuss their properties and the implementation techniques to use them in security applications. We first present two novel PUF structures. The first one, called “Loop PUF” is a delay based PUF which relies on the comparison of delay measurements of identical serial delay chains. The major contribution brought by the use of this structure is its implementation simplicity on both ASIC and FPGA platforms, and its flexibility as it can be used for reliable authentication or key generation. The second proposed structure is a ring-oscillator based PUF cells “TERO PUF”. It exploits the oscillatory metastability of cross-coupled elements, and can also be used as True Random Number Generator (TRNG). More precisely, the PUF response takes advantage from the introduced oscillatory metastability of an SR flip-flop when the S and R inputs are connected to the same input signal. Experimental results show the high performance of these two proposed PUF structures. Second, in order to fairly compare the quality of different delay based PUFs, we propose a specific characterization method. It is based on statistical measurements on basic delay elements. The main benefit of this method is that it allows the designer to be sure that the PUF will meet the expected performances before its implementation and fabrication. Finally, Based on the unclonability and unpredictability properties of the PUFs, we present new techniques to perform “loop PUF” authentication and cryptographic key generation. Theoretical and experimental results show the efficiency of the introduced techniques in terms of complexity and reliabilityLes fonctions non clonables physiquement, appelées PUF (Physically Unclonable Functions), représentent une technologie innovante qui permet de résoudre certains problèmes de sécurité et d’identification. Comme pour les empreintes humaines, les PUF permettent de différencier des circuits électroniques car chaque exemplaire produit une signature unique. Ces fonctions peuvent être utilisées pour des applications telles que l’authentification et la génération de clés cryptographiques. La propriété principale que l’on cherche à obtenir avec les PUF est la génération d’une réponse unique qui varie de façon aléatoire d’un circuit à un autre, sans la possibilité de la prédire. Une autre propriété de ces PUF est de toujours reproduire, quel que soit la variation de l’environnement de test, la même réponse à un même défi d’entrée. En plus, une fonction PUF doit être sécurisée contre les attaques qui permettraient de révéler sa réponse. Dans cette thèse, nous nous intéressons aux PUF en silicium profitant des variations inhérentes aux technologies de fabrication des circuits intégrés CMOS. Nous présentons les principales architectures de PUF, leurs propriétés, et les techniques mises en œuvre pour les utiliser dans des applications de sécurité. Nous présentons d’abord deux nouvelles structures de PUF. La première structure appelée “Loop PUF” est basée sur des chaînes d’éléments à retard contrôlés. Elle consiste à comparer les délais de chaînes à retard identiques qui sont mises en série. Les points forts de cette structure sont la facilité de sa mise en œuvre sur les deux plates-formes ASIC et FPGA, la grande flexibilité pour l’authentification des circuits intégrés ainsi que la génération de clés de chiffrement. La deuxième structure proposée “TERO PUF” est basée sur le principe de cellules temporairement oscillantes. Elle exploite la métastabilité oscillatoire d’éléments couplés en croix, et peut aussi être utilisée pour un générateur vrai d’aléas (TRNG). Plus précisément, la réponse du PUF profite de la métastabilité oscillatoire introduite par une bascule SR lorsque les deux entrées S et R sont connectées au même signal d’entrée. Les résultats expérimentaux montrent le niveau de performances élevé des deux structures de PUF proposées. Ensuite, afin de comparer équitablement la qualité des différentes PUF à retard, nous proposons une méthode de caractérisation spécifique. Elle est basée sur des mesures statistiques des éléments à retard. Le principal avantage de cette méthode vient de sa capacité à permettre au concepteur d’être sûr que la fonction PUF aura les performances attendues avant sa mise en œuvre et sa fabrication. Enfin, en se basant sur les propriétés de non clonabilité et de l’imprévisibilité des PUF, nous présentons de nouvelles techniques d’authentification et de génération de clés de chiffrement en utilisant la “loop PUF” proposée. Les résultats théoriques et expérimentaux montrent l’efficacité des techniques introduites en termes de complexité et de fiabilit
Design of hardware-orientated security towards trusted electronics.
While the Internet of Things (IoT) becomes one of the critical components in the
cyber-physical system of industry 4.0, its root of trust still lacks consideration. The
purpose of this thesis was to increase the root of trust in electronic devices by
enhance the reliability, testability, and security of the bottom layer of the IoT
system, which is the Very Large-Scale Integration (VLSI) device. This was
achieved by implement a new class of security primitive to secure the IJTAG
network as an access point for testing and programming. The proposed security
primitive expands the properties of a Physically Unclonable Function (PUF) to
generate two different responses from a single challenge. The development of
such feature was done using the ring counter circuit as the source of randomness
of the PUF to increase the efficiency of the proposed PUF. The efficiency of the
newly developed PUF was measured by comparing its properties with the
properties of a legacy PUF. The randomness test done for the PUF shows that it
has a limitation when implemented in sub-nm devices. However, when it was
implemented in current 28nm silicon technology, it increases the sensitivity of the
PUF as a sensor to detect malicious modification to the FPGA configuration file.
Moreover, the efficiency of the developed bimodal PUF increases by 20.4%
compared to the legacy PUF. This shows that the proposed security primitive
proves to be more dependable and trustworthy than the previously proposed
approach.Samie, Mohammad (Associate)PhD in Transport System
Hardware design of cryptographic algorithms for low-cost RFID tags
MenciĂłn Internacional en el tĂtulo de doctorRadio Frequency Identification (RFID) is a wireless technology for automatic identification that has experienced a notable growth in the last years. RFID is an important part of the new trend named Internet of Things (IoT), which describes a near future where all the objects are connected to the Internet and can interact between them. The massive deployment of RFID technology depends on device costs and dependability. In order to make these systems dependable, security needs to be added to RFID implementations, as RF communications can be accessed by an attacker who could extract or manipulate private information from the objects. On the other hand, reduced costs usually imply resource-constrained environments.
Due to these resource limitations necessary to low-cost implementations, typical cryptographic primitives cannot be used to secure low-cost RFID systems. A new concept emerged due to this necessity, Lightweight Cryptography. This term was used for the first time in 2003 by Vajda et al. and research on this topic has been done widely in the last decade. Several proposals oriented to low-cost RFID systems have been reported in the literature. Many of these proposals do not tackle in a realistic way the multiple restrictions required by the technology or the specifications imposed by the different standards that have arose for these technologies. The objective of this thesis is to contribute in the field of lightweight cryptography oriented to low-cost RFID tags from the microelectronics point of view.
First, a study about the implementation of lightweight cryptographic primitives is presented . Specifically, the area used in the implementation, which is one of the most important requirements of the technology as it is directly related to the cost. After this analysis, a footprint area estimator of lightweight algorithms has been developed. This estimator calculates an upper-bound of the area used in the implementation. This estimator will help in making some choices at the algorithmic level, even for designers without hardware design skills.
Second, two pseudo-random number generators have been proposed. Pseudorandom number generators are essential cryptographic blocks in RFID systems.
According to the most extended RFID standard, EPC Class-1 Gen-2, it is mandatory to include a generator in RFID tags. Several architectures for the two proposed generators have been presented in this thesis and they have been integrated in two authentication protocols, and the main metrics (area, throughput and power consumption) have been analysed.
Finally, the topic of True Random Number Generators is studied. These generators are also very important in secure RFID, and are currently a trending research line. A novel generator, presented by Cherkaoui et al., has been evaluated under different attack scenarios. A new true random number generator based on coherent sampling and suitable for low-cost RFID systems has been proposed.La tecnologĂa de IdentificaciĂłn por Radio Frecuencia, más conocida por sus siglas en inglĂ©s RFID, se ha convertido en una de las tecnologĂas de autoidentificaciĂłn más importantes dentro de la nueva corriente de identificaciĂłn conocida como Internet de las Cosas (IoT). Esta nueva tendencia describe un futuro donde todos los objetos están conectados a internet y son capaces de identificarse ante otros objetos. La implantaciĂłn masiva de los sistemas RFID está hoy en dĂa limitada por el coste de los dispositivos y la fiabilidad. Para que este tipo de sistemas sea fiable, es necesario añadir seguridad a las implementaciones RFID, ya que las comunicaciones por radio frecuencia pueden ser fácilmente atacadas y la informaciĂłn sobre objetos comprometida. Por otro lado, para que todos los objetos estĂ©n conectados es necesario que el coste de la tecnologĂa de identificaciĂłn sea muy reducido, lo que significa una gran limitaciĂłn de recursos en diferentes ámbitos.
Dada la limitaciĂłn de recursos necesaria en implementaciones de bajo coste, las primitivas criptográficas tĂpicas no pueden ser usadas para dotar de seguridad a un sistema RFID de bajo coste. El concepto de primitiva criptográfica ligera fue introducido por primera vez 2003 por Vajda et al. y ha sido desarrollado ampliamente en los Ăşltimos años, dando como resultados una serie de algoritmos criptográficos ligeros adecuados para su uso en tecnologĂa RFID de bajo coste. El principal problema de muchos de los algoritmos presentados es que no abordan de forma realista las mĂşltiples limitaciones de la tecnologĂa. El objetivo de esta tesis es el de contribuir en el campo de la criptografĂa ligera orientada a etiquetas RFID de bajo coste desde el punto de vista de la microelectrĂłnica.
En primer lugar se presenta un estudio de la implementaciĂłn de las primitivas criptográficas ligeras más utilizadas, concretamente analizando el área ocupado por dichas primitivas, ya que es uno de los parámetros crĂticos considerados a la hora de incluir dichas primitivas criptográficas en los dispositivos RFID de bajo coste. Tras el análisis de estas primitivas se ha desarrollado un estimador de área para algoritmos criptográficos ultraligeros que trata de dar una cota superior del área total ocupada por el algoritmo (incluyendo registros y lĂłgica de control). Este estimador permite al diseñador, en etapas tempranas del diseño y sin tener ningĂşn conocimiento sobre implementaciones, saber si el algoritmo está dentro de los lĂmites de área mpuestos por la tecnologĂa RFID.
TambiĂ©n se proponen 2 generadores de nĂşmeros pseudo-aleatorios. Estos generadores son uno de los bloques criptográficos más importantes en un sistema RFID. El estándar RFID más extendido entre la industria, EPC Class-1 Gen-2, establece el uso obligatorio de dicho tipo de generadores en las etiquetas RFID. Los generadores propuestos han sido implementados e integrados en 2 protocolos de comunicaciĂłn orientados a RFID, obteniendo buenos resultados en las principales caracterĂsticas del sistema.
Por Ăşltimo, se ha estudiado el tema de los generadores de nĂşmeros aleatorios. Este tipo de generadores son frecuentemente usados en seguridad RFID. Actualmente esta lĂnea de investigaciĂłn es muy popular. En esta tesis, se ha evaluado la seguridad de un novedoso TRNG, presentado por Cherkaoui et al., frente ataques tĂpicos considerados en la literatura. Además, se ha presentado un nuevo TRNG de bajo coste basado en la tĂ©cnica de muestreo por pares.Programa Oficial de Doctorado en IngenierĂa ElĂ©ctrica, ElectrĂłnica y AutomáticaPresidente: Teresa Riesgo Alcaide.- Secretario: Emilio OlĂas Ruiz.- Vocal: Giorgio di Natal
Delay-based true random number generator in sub-nanomillimeter IoT devices
True Random Number Generators (TRNGs) use physical phenomenon as their source of randomness. In electronics, one of the most popular structures to build a TRNG is constructed based on the circuits that form propagation delays, such as a ring oscillator, shift register, and routing paths. This type of TRNG has been well-researched within the current technology of electronics. However, in the future, where electronics will use sub-nano millimeter (nm) technology, the components become smaller and work on near-threshold voltage (NTV). This condition has an effect on the timing-critical circuit, as the distribution of the process variation becomes non-gaussian. Therefore, there is an urge to assess the behavior of the current delay-based TRNG system in sub-nm technology. In this paper, a model of TRNG implementation in sub-nm technology was created through the use of a specific Look-Up Table (LUT) in the Field-Programmable Gate Array (FPGA), known as SRL16E. The characterization of the TRNG was presented and it shows a promising result, in that the delay-based TRNG will work properly, with some constraints in sub-nm technolog
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