Design-for-test structure to facilitate test vector application with low performance loss in non-test mode.

A switching based circuit is described which allows application of voltage test vectors to internal nodes of a chip without the problem of backdriving. The new circuit has low impact on the performance of an analogue circuit in terms of loss of bandwidth and allows simple application of analogue test voltages into internal nodes. The circuit described facilitates implementation of the forthcoming IEEE 1149.4 DfT philosophy [1]

Breathing metabolic simulator

Breathing metabolic simulator design for test and evaluation of breathing and life support equipmen

Design for Test and Hardware Security Utilizing Tester Authentication Techniques

Design-for-Test (DFT) techniques have been developed to improve testability of integrated circuits. Among the known DFT techniques, scan-based testing is considered an efficient solution for digital circuits. However, scan architecture can be exploited to launch a side channel attack. Scan chains can be used to access a cryptographic core inside a system-on-chip to extract critical information such as a private encryption key. For a scan enabled chip, if an attacker is given unlimited access to apply all sorts of inputs to the Circuit-Under-Test (CUT) and observe the outputs, the probability of gaining access to critical information increases. In this thesis, solutions are presented to improve hardware security and protect them against attacks using scan architecture. A solution based on tester authentication is presented in which, the CUT requests the tester to provide a secret code for authentication. The tester authentication circuit limits the access to the scan architecture to known testers. Moreover, in the proposed solution the number of attempts to apply test vectors and observe the results through the scan architecture is limited to make brute-force attacks practically impossible. A tester authentication utilizing a Phase Locked Loop (PLL) to encrypt the operating frequency of both DUT/Tester has also been presented. In this method, the access to the critical security circuits such as crypto-cores are not granted in the test mode. Instead, a built-in self-test method is used in the test mode to protect the circuit against scan-based attacks. Security for new generation of three-dimensional (3D) integrated circuits has been investigated through 3D simulations COMSOL Multiphysics environment. It is shown that the process of wafer thinning for 3D stacked IC integration reduces the leakage current which increases the chip security against side-channel attacks

A low-speed BIST framework for high-performance circuit testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addresse

Determining DfT Hardware by VHDL-AMS Fault Simulation for Biological Micro-Electronic Fluidic Arrays

The interest of microelectronic fluidic arrays for biomedical applications, like DNA determination, is rapidly increasing. In order to evaluate these systems in terms of required Design-for-Test structures, fault simulations in both fluidic and electronic domains are necessary. VHDL-AMS can be used successfully in this case. This paper shows a highly testable architecture of a DNA Bio-Sensing array, its basic sensing concept, fluidic modeling and sensitivity analysis. The overall VHDL-AMS fault simulation of the system is shown

An integrated framework to support remote IEEE 1149.1 /1149.4 design for test experiments

Remote experiments for academic purposes can only achieve their educational goals if an appropriate framework is able to provide a basic set of features, namely remote laboratory management, collaborative learning tools and content management and delivery. This paper presents a framework developed to support remote experiments in a design for test class offered to final year students at the Electrical and Computer Engineering degree at the University of Porto. The proposed solution combines a test language command interpreter and various virtual instruments (VIs), with a demonstration board that comprises a boundary-scan IEEE 1149.1 / 1149.4 test infrastructure. The experiments are presented as embedded learning objects, with no distinction from other e-learning contents (e.g. lessons, lecture notes, etc.)

Design for test and qualification through activity-based modelling in product architecture design

Test and qualification (T&Q) phases take a significant portion of the time to market for critical products in the space industry, especially when introducing new technologies. Since T&Q are treated as standard procedures, they tend to be independent of the architectural design phases and kept away from design decisions. However, when introducing new technologies, qualification procedures may differ from those established in regular design scenarios, and the estimation of qualification costs and duration is problematic. There is a lack of design for qualification methods capable of modelling these activities in early phases and use those models to support the architecture design of products with affordable test and qualification phases. In this article, a computer-assisted, model-based design method to model T&Q activities concerning early product architecture designs is proposed. Product architecture alternatives, test schedules and cost are connected through the quantification of T&Q drivers and driver rates. The design method is demonstrated using a case study about electric propulsion for satellites. The method is applicable for design situations where the choice of technology has a strong dependence on the qualification procedure

Design for test and qualification through activity-based modelling in product architecture design

Test and qualification (T&Q) phases take a significant portion of the time to market for critical products in the space industry, especially when introducing new technologies. Since T&Q are treated as standard procedures, they tend to be independent of the architectural design phases and kept away from design decisions. However, when introducing new technologies, qualification procedures may differ from those established in regular design scenarios, and the estimation of qualification costs and duration is problematic. There is a lack of design for qualification methods capable of modelling these activities in early phases and use those models to support the architecture design of products with affordable test and qualification phases. In this article, a computer-assisted, model-based design method to model T&Q activities concerning early product architecture designs is proposed. Product architecture alternatives, test schedules and cost are connected through the quantification of T&Q drivers and driver rates. The design method is demonstrated using a case study about electric propulsion for satellites. The method is applicable for design situations where the choice of technology has a strong dependence on the qualification procedure

Testing conformance of a deterministic implementation against a non-deterministic stream X-machine

Stream X-machines are a formalisation of extended finite state machines that have been used to specify systems. One of the great benefits of using stream X-machines, for the purpose of specification, is the associated test generation technique which produces a test that is guaranteed to determine correctness under certain design for test conditions. This test generation algorithm has recently been extended to the case where the specification is non-deterministic. However, the algorithms for testing from a non-deterministic stream X-machine currently have limitations: either they test for equivalence, rather than conformance or they restrict the source of non-determinism allowed in the specification. This paper introduces a new test generation algorithm that overcomes both of these limitations, for situations where the implementation is known to be deterministic