A switching based circuit is described which allows application of voltage test vectors to internal nodes of a chip without the problem of backdriving. The new circuit has low impact on the performance of an analogue circuit in terms of loss of bandwidth and allows simple application of analogue test voltages into internal nodes. The circuit described facilitates implementation of the forthcoming IEEE 1149.4 DfT philosophy [1]

Bratt, Adrian

Dorey, A. P.

Harvey, R. J. A.

Richardson, A. M. D.

English

Lancaster E-Prints

smaller cavity efficiency and a stronger influence of third order dispersion due to the internal grating compressor. -8 2 b , x l O c r n / W  r -0  15 -0 I -0 0 5  0 d 0 0 5  0 1 0  0 15 0 20 a?, pslnrn Fig. 3 External compressor dispersion at optimum as function of intra- cavity group velocity dispersion 0 experiment ~ numerical simulations for different b, values - - - _  analytical calculation of minimum dispersion Mode l l ing :  Laser-diode modelocking was analysed using the master equation approach developed by Haus [a]. Intracavity dispersion as well as instantaneous net-gain saturation and self-phase modulation effects were included as in the work of Martinez et al .  [?‘I. Closed-form analytical solutions of pulse parameters could then be obtained. Numerical simulations were performed in parallel to test the stability of the solutions. The details of our analysis are given elsewhere [8]. Two well-known peculiarities of semiconductor laser media as compared to other systems are: large refractive index (phase) variations associated with gain/absorption variations, and strong gain/absorption saturation detected in short time scales [SI. Considering that quadratic variations of phase with energy (-I“ terms in Reference 7) occur with a sign opposite to those of net gain (g” term), we theoretically verified that modelocking could be only achieved for normal intracavity GVD. As a second result, we found that instantaneous net- gain saturation (b, term in Reference 7) was responsible for the dispersion offset measured at minimum intracavity GVD. For strong chirp, the minimum intracavity GVD and dis- persion offset were found to be correctly described by the following formulas: where azo = --Zn,Y”go/k, is the minimum GVD in the absence of fast gain saturation, a, is the available bandwidth and k,, k, are related to the go, g’, g” coefficients appearing in the series expansion of net gain with energy (k, =g” - 49,. g” and k, = g” - 69,. 9”). The theoretical evolution of Do,, predicted by eqns. 1 and 2 is reported in Fig. 3 for a, = 7 x 10-4ps2, go = -0.6, g’ = 0.3pJ-’, g” = -O.OZPJ-~ and -I“ = -2.59’’ (dashed curve). Full curves are numerical calculations of the external compressor disper- sion at optimum. As seen, there is an excellent agreement between calculations and experiments for b, = -0.15 x 10-8cmZ/W, which is’close to what can be deduced from previous experiments [SI. Note the absence of dispersion offset when only energetic (slow) variations of laser net gain and phase are considered (b, = 0). The weak dependence of the curve slope with b, is also remarkable; this can be reason- ably approximated by 2(g” - 39, . g”)/(go . 8“). Conclusion: Passive (hybrid) modelocking of laser diodes in an extended cavity with high tunable group velocity dispersion has been demonstrated. The evolution of pulse compressibility with intracavity dispersion has revealed the important role of instantaneous laser net gain saturation even for modelocked pulses in the picosecond time scale. The requirement of posi- tive dispersion seems to be related to the self-phase modula- tion of the laser medium. 0 IEE 1993 15th June 1993 A. Azouz, N. Stelmakh and J.-M. Lourtioz (Institut d’Efectronique Fondamentafe U R A  22 du CNRS,  Uniuersite Paris X I ,  Bat. 220,91405 Orsay Cedex, France) Refereaces SCHRANS, I., SALVATORE, R. A., SANDERS, S., and YAIUV, A.: ‘Sub- picosecond (3201s) pulses from moddocked external cavity two- section multiquantum well lasers’, Electron. Lett., 1992, 28, pp. 1480-148 1 STELMAKH, N., and WURTIOZ, I.-M.: ‘230fs high-power pulses from conventional mode-locked laser diodes with ion implantation’, Electron. Lett., 1993.29, pp. 16&161 SILBUIBUIG, Y., and shnni, P. w.: ‘Subpicosewnd pulses from a mode-locked semiconductor laser’, IEEE J .  Quantum Electron., 1986, QE22. pp. 759-761 DAKIS, N. c., SILBERBWG, v., -AOE I. P., and A L P H O ~  G.  A.: ‘High-power ultrafast laser diodes’, IEEE J .  Quantum Efectron., MARTINEZ 0. E.: ‘3000 times grating compressor with positive group velocity dispersion: application to fiber compensation in 1.3-1.6pm region’, IEEE J. Quantum Electron., 1987, Q E D ,  pp. 59-64 mu% H. A.: Theory of modelocking with a slow saturable absorber’, IEEE J. Quantum Electron., 1975, Q E l l ,  pp. 736-746 MARTINEZ, 0. a, FORK, R. L., and GORDON, I. P.: ‘Theory of passively mode-locked laser for the case of a nonlinear complex- propagation dicient’, J. Opt. Sw. Am. E, 1985.2. pp. 753-760 AZOUZ, A., SmLMAKH, N., and munnoZ, I.-M.: submitted to IEEE J. Quantum Electron. HULWGRW, c. T., and IPPEN, a P.: ‘Ultrafast refractive index dynamics in AlGaAs diode laser amplifiers’, Appl. Phys. Lett., 1991.9, pp. 635-631 DeLP(m, P. I., FWREZ, L. T., SIOFFl& N. G., GMI”F,R, I. I., ANDREA- 1992, QEW pp. 220-2219 DESIGN-FOR-TEST STRUCTURE TO FACILITATE TEST VECTOR APPLICATION WITH LOW PERFORMANCE LOSS IN A. H. Bratt, R. J. Harvey, A. P. Dorey and A. M. D. Richardson NON-TEST MODE Indexing term: Designfor testability A switching based circuit is described which allows applica- tion of voltage test vectors to internal nodes of a chip without the problem of backdriving. The new circuit has low impact on the performance of an analogue circuit in terms of loss of bandwidth and allows simple application of analogue test voltages into internal nodes. The circuit described facili- tates implementation of the forthcoming IEEE 1149.4 D!T philosophy [ 13. Introduct ion:  A DfI  philosophy must simultaneously satisfy several criteria of which three major elements are [2]: (i) Control and observation of deeply embedded nodes must be possible to veriry circuit functionality and detect fabrica- tion defects by the application and observation of test vectors. (ii) Performance loss must be minimal in normal (non-test) operating mode. In particular, loss of bandwidth must be avoided and area overhead must not be excessive. (iii) Migration of the testing problem from device level to chip level should be possible and this process should be amenable to automation. 1438 ELECTRONICS LETTERS 5th August 1993 Vol. 29 No. 16 Authorized licensed use limited to: Lancaster University Library. Downloaded on December 5, 2008 at 05:33 from IEEE Xplore.  Restrictions apply.It is assumed that a design may be divided into a number of blocks which perform identiliable functions and may be tested in isolation. The process of testing then becomes one of appli- cation of test voltages between blocks and observation of the subsequent output of the block on the proceeding signal path. A major problem with this methodology is that blocks often have low output impedance which frustrates attempts at directly controlling voltage levels between them due to the low impedance of the node, a phenomenon known as back- driving. It has been proposed that a pass transistor structure may be used to isolate an inter-block node from the output stage of the previous block [3], but the presence of switching tran- sistors in the signal path during non-test mode may have serious performance repercussions in limiting the bandwidth. Fig. 1 shows a circuit designed to prevent backdriving based on that proposed in Reference 3 and traces (i) and (ii) of Fig. 3 T Fig. 1 Complementary pass tramistors used to prevent backdriuing represent the bandwidth loss of an operational amplifier without and with, respectively, the complementary switch added as in Fig. 1. Clearly the performance impact is signifi- cant and the effect may easily be demonstrated to be much more severe for a circuit which as a sensitive output (sensitive in the sense of having low drive power, high loading or a low impedance path to ground). A circuit is presented in this Letter which overcomes the backdriving problems associated with attempts to directly drive inter-block nodes and has much less impact on the bandwidth of the circuit in non-test mode. D j 7  switching circuit operational amplifier: Fig. 2 shows a schematic diagram of an operational amplifier with two stan- dard input stages of the type shown in Reference 4 and a common output stage. The digital input signal 'test' and its complement 'testbar' may be used to connect either of the input stages to the output stage. Note that the field effect transistors (FET) which perform the switching action (M1 and M2) are inserted in small-signal paths rather than large signal paths. The source and drain terminals of M1 and M2 are maintained at a common voltage of approximately V, - 0.8 V so the need for a complementary switch as in Fig. 1, is obviated. Note also that M1 and M2 need only have an aspect ratio of 10/3 because they carry a typical current of only 8 pA with a 1 MHz sinusoid input signal of 1 V peak to If input stage B is selected (test = '0') then the operational amplifier performs its normal function with minimal loss of bandwidth. Trace (iii) of Fig. 3 represents the Bode plot of this amplifier in non-test mode. Clearly the bandwidth change peak. 2.01 8 10 4 6  Hz 0 2  1301131 Fig. 3 Bode plot of operational amplijier with no DjT structures added, proposed I E E E  1149.4 DjT structures added, and new structures added (i) no added DIT structures (ii) proposed IEEE 1149.4 DIT structures added ( i )  new DIT structures added with respect to the unloaded case (trace (i)) is greatly reduced from that seen in trace (U). Increasing the aspect ratio of the switching FETs M1 and M2 will further reduce the band- width degradation if necessary. If input stage A is selected then voltages that are applied to terminal 'vector' will re-appear at the output of the amplifier subject to the usual limitations of an operational amplifier such as offset voltage, slew rate limitation etc. The FETs in stage A may be made very much smaller than those of input stage B because, in general, the performance of this input stage for testing purposes is not usually required to be as high as for stage B. The problem of backdriving in the test mode is no longer present with this circuit configuration; the inter-block test vector voltage is produced by the output stage of the oper- ational amplifier rather than in opposition to it. Conclusion: A switching based circuit has been described which allows a DfT scheme to be implemented with little loss of bandwidth and a minimal area overhead. The problem of backdriving is effectively obviated because the output stage for both test and non-test modes is the same. A cell-by-cell testing strategy is possible with the proposed circuit under the limitation that it has been assumed that the majority of blocks 186um/ 5um out refn g u m /  5um L30112j "ss Fig. 2 Proposed operational amplijier circuit with switchable input stages for application of voltage test vectors ELECTRONICS LE77ERS 5th August 1993 Vol. 29 No. 16 1439 I 1  ~~~ Authorized licensed use limited to: Lancaster University Library. Downloaded on December 5, 2008 at 05:33 from IEEE Xplore.  Restrictions apply.. I  have an operational amplifier driving the output node. Injec- tion of test vectors into interblock nodes is performed easily and with little loading of the test vector voltage. Acknowledgment: The work described here was supported by SERC and the EUROCHIP organisation. Thanks also go to C. Thomas of MCE, Tewkesbury for many valuable dis- cussions. 0 IEE 1993 7th June 1993 A. H. Bratt, R. J. Harvey, A. P. Dorey and A. M. D. Richardson (Engineering School, SECAMS, Lancaster University LA1 4YR, United Kingdom) Refereoces THATCHER, c., et al.: ‘1 149.4 mixed-signal measurement proposal’. ITC. 1993 z&nu, T.: Philips Research Laboratories, Eindhoven, The Netherlands: Personal Communication WLKINS, B. R., et al.: ‘Towards a mixed-signal testability bus stan- dard‘. ETC, April 1993 ALLEN, P. E., and HoLBERG, R. H.: ‘CMOS analog circuit design’ (Holt, Rinehart and Winston, New York, 1987). p. 330 ANALYSIS OF SKELETON JUNCTIONS IN 3 x 3 WINDOWS E. R. Davies and D. Celano Indexing t e r m :  Image processing, Pattern recognition The Letter studies the formation and analysis of skeletons in binary images. Particular emphasis is placed on the concept of crossing number which is found to be subtly differe-nt when testing a point known to be on a skeleton and testing whether a point is on a skeleton: these ideas are applied to the elimination of noise spurs from skeletons. Introduction: The skeleton of a binary figure can be defined as a connected graph that runs along the medial lines of the limbs of the figure [ l ] .  It is a useful concept in that its form reflects the general shape of a figure (including all its holes and limbs), and in particular its connectedness parallels that of the figure. Analysis of skeletons involves particularly location and classification of ‘nodes’ (including junctions and line ends) and measurement of limb lengths and orientations. Although skeletons are important for the analysis of shapes in binary images, a number of intricacies arise in the forma- tion and analysis of skeletons. This Letter considers skeleton junction analysis and studies the elimination of noise spurs from skeletons: the immediate motivation for this arose from our own work on structure in textures. Crossing number and skeleton formation: Both the formation and the analysis of skeletons are aided by the concept of a crossing number x, the basic idea of which is to count the number of changes from white to black and black to white on proceeding once around a given pixel [l, 21. However, the concept is complicated in its implementation because the defi- nition of connectedness on a binary lattice involves a funda- mental difficulty. In particular, diagonally adjacent 1s have to be regard as joined, but diagonally adjacent Os must not be; this ‘8-connectedness’ ddinition overcomes the problem that the background Os are simultaneously adjacent to each other and separated from each other by the foreground Is in the configuration 1440 Hence [I, 21, x has to be redefined as the number of effective changes from white to black and black to white on going around a given pixel, and implemented in a 3 x 3 window as x = U(A1 # A3) + U(A3 # AS) + U(A5 # A7) + U(A7 # A l )  + 2 [ U ( i  AI & A2 & 7.43) + U ( i  A3 & A4 & i A 5 )  + U ( i  A5 & A6 & i A7) + U ( i  A7 & A8 & i Al)] (1) where the 3 x 3 window notation is: A5 A0 A1 A6 A7 A8 the window values A0 to A8 are all Boolean Os and Is, ‘&‘ is the logical AND function, $1’ is the logical NOT function, and the ‘unity’ function U( .) converts Boolean values 0 and 1 to numerical values 0 and 1, respectively. Also of relevance for skeleton formation and analysis is the u-function: U = U(A1) + U(A2) + U(A3) + U(A4) + U(A5) + U(A6) + U(A7) + U(A8) (2) A simple parallel thinning algorithm is now [ 2 ] :  suc- cessively remove boundary North, South, East and West points until no further change occurs, but only at points for which x = 2 and U # 1. The first of these two conditions pre- vents points from being removed when this would affect con- nectedness, and the second condition prevents limbs from being shortened. Although many more complex thinning algo- rithms exist [l, 3 , 4 ] ,  this simple one shows the role played by crossing number in skeleton formation. Skeleton analysis potentially involves examination of local crossing number values, e.g. x = 4, x = 6 or 8, x = 2, x = 0 might indicate respectively a ‘normal’ skeleton point, a junc- tion, a line end, and a point skeleton. We amend this view of the situation below. Analysis of skeleton junctions;: We have found that although crossing number is a useful concept for skeleton formation, it has restricted value when analysing skeletons. Consider the following instance: -1 This apparently corresponds to a T-junction, but its crossing number value of 4 indicates that it is a ‘normal‘ skeleton point. In fact both interpretations are wrong, assuming this is known to be a point on a skeleton; thus the A3 value of 1 can only arise if there is a point North-East of it. Similarly the AI value of 1 can only arise if there is a point East, NE or SE of it. In fact all window border points that are 1s must corre- spond to different lies joining the centre pixel; this clearly includes lone diagonal points (e.g. the A6 point in the above example). Thus the number of lines arriving at a given point must be U, and we can consistently (see the Introduction) deiine the effective crossing number on a skeleton as being twice this, i.e. be, = 25. We amplify this statement by giving two examples of 5 x 5 windows for which the inner 3 x 3 windows have U-values of 4 and 8, respectively: 1 0 0 1 0  0 1 1 0 0  0 0 1 1 1  0 1 0 0 0  71 0 0 0 0  1 0 1 0 1  0 1 1 1 0  1 1 1 1 1  0 1 1 1 0  r1 0 1 0 1  ELECTRONICS LE77ERS 5th August 1993 Vol. 29 No. 16 ~ I 1  Authorized licensed use limited to: Lancaster University Library. Downloaded on December 5, 2008 at 05:33 from IEEE Xplore.  Restrictions apply.

Design-for-test structure to facilitate test vector application with low performance loss in non-test mode.

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Design-for-test structure to facilitate test vector application with low performance loss in non-test mode.

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