Improved Physical Design for Manufacturing Awareness and Advanced VLSI

Increasing challenges arise with each new semiconductor technology node, especially in advanced nodes, where the industry tries to extract every ounce of benefit as it approaches the limits of physics, through manufacturing-aware design technology co-optimization and design-based equivalent scaling. The increasing complexity of design and process technologies, and ever-more complex design rules, also become hurdles for academic researchers, separating academic researchers from the most up-to-date technical issues.This thesis presents innovative methodologies and optimizations to address the above challenges. There are three directions in this thesis: (i) manufacturing-aware design technology co-optimization; (ii) advanced node design-based equivalent scaling; and (iii) an open source academic detailed routing flow.To realize manufacturing-aware design technology co-optimization, this thesis presents two works: (i) a multi-row detailed placement optimization for neighbor diffusion effect mitigation between neighboring standard cells; and (ii) a post-routing optimization to generate 2D block mask layout for dummy segment removal in self-aligned multiple patterning.To achieve advanced node design-based equivalent scaling, this thesis presents two improved physical design methodologies: (i) a post-placement flop tray generation approach for clock power reduction; and (ii) a detailed placement approach to exploit inter-row M1 routing for congestion and wirelength reduction.To address the increasing gap between academia and industry, this thesis presents two works toward an open source academic detailed routing flow: (i) a complete, robust, scalable and design ruleaware dynamic programming-based pin access analysis framework; and (ii) TritonRoute – the open source detailed router that is capable of delivering DRC-clean detailed routing solutions in advanced nodes.This thesis concludes with a summary of its contributions and open directions for future research

Alternative Lithographic Methods for Variable Aspect Ratio Vias

The foundation of semiconductor industry has historically been driven by scaling. Device size reduction is enabled by increased pattern density, enhancing functionality and effectively reducing cost per chip. Aggressive reductions in memory cell size have resulted in systems with diminishing area between parallel bit/word lines. This affords an even greater challenge in the patterning of contact level features that are inherently difficult to resolve because of their relatively small area, a product of their two domain critical dimension image. To accommodate these trends there has been a shift toward the implementation of elliptical contact features. This empowers designers to maximize the use of free space between bit/word lines and gate stacks while preserving contact area; effectively reducing the minor via axis dimension while maintaining a patternable threshold in increasingly dense circuitry. It is therefore critical to provide methods that enhance the resolving capacity of varying aspect ratio vias for implementation in electronic design systems. This work separately investigates two unique, non-traditional lithographic techniques in the integration of an optical vortex mask as well as a polymer assembly system as means to augment ellipticity while facilitating contact feature scaling. This document affords a fundamental overview of imaging theory, details previous literature as to the technological trends enabling the resolving of contact features and demonstrates simulated & empirical evidence that the described methods have great potential to extend the resolution of variable aspect ratio vias using lithographic technologies

Biomimetic nanostructured surfaces for antireflection in photovoltaics

A key consideration in the design of any solar cell is the reduction of reflectance from the top surface. Traditional thin film antireflection schemes are being challenged by new techniques that involve texturing on the subwavelength scale to form ‘moth-eye’ arrays, so called because they are inspired by Nature’s answer to unwanted reflections, the arrays of pillars found on the eyes and wings of some species of moth. In this work, a new method is presented for the optimization of thin film coatings that accounts for the angular and spectral variations in incident solar radiation from sunrise to sunset. This approach is then extended to silicon moth-eye arrays to assess how effectively these surfaces can provide antireflection for silicon solar cells over a full day. The reflectance spectra of moth-eye surfaces are found to depend on the period of the arrays and the height and shape of the pillars, and consequently these parameters can be optimized for the solar spectrum. Simulations predict that replacing an optimized double layer thin film coating with a moth-eye array could increase the full day cell performance by 2% for a laboratory cell and 3% for an encapsulated cell. Compared to a perfectly transmitting interface, this corresponds to losses in short circuit current of only 5.3% and 0.6% for a laboratory and an encapsulated cell, respectively. Furthermore, fabrication of silicon moth-eye arrays by electron beam lithography and dry etching leads to predicted percentage losses at peak irradiance, compared to an ideal antireflective surface, of only 1%. The potentially more scalable technique of nanoimprint lithography is also used to fabricate antireflective moth-eye arrays in silicon, over areas as large as 1 cm2, demonstrating great potential for stealth and antiglare applications in addition to photovoltaics

DFM Techniques for the Detection and Mitigation of Hotspots in Nanometer Technology

With the continuous scaling down of dimensions in advanced technology nodes, process variations are getting worse for each new node. Process variations have a large influence on the quality and yield of the designed and manufactured circuits. There is a growing need for fast and efficient techniques to characterize and mitigate the effects of different sources of process variations on the design's performance and yield. In this thesis we have studied the various sources of systematic process variations and their effects on the circuit, and the various methodologies to combat systematic process variation in the design space. We developed abstract and accurate process variability models, that would model systematic intra-die variations. The models convert the variation in process into variation in electrical parameters of devices and hence variation in circuit performance (timing and leakage) without the need for circuit simulation. And as the analysis and mitigation techniques are studied in different levels of the design ow, we proposed a flow for combating the systematic process variation in nano-meter CMOS technology. By calculating the effects of variability on the electrical performance of circuits we can gauge the importance of the accurate analysis and model-driven corrections. We presented an automated framework that allows the integration of circuit analysis with process variability modeling to optimize the computer intense process simulation steps and optimize the usage of variation mitigation techniques. And we used the results obtained from using this framework to develop a relation between layout regularity and resilience of the devices to process variation. We used these findings to develop a novel technique for fast detection of critical failures (hotspots) resulting from process variation. We showed that our approach is superior to other published techniques in both accuracy and predictability. Finally, we presented an automated method for fixing the lithography hotspots. Our method showed success rate of 99% in fixing hotspots

Standard cell optimization and physical design in advanced technology nodes

Integrated circuits (ICs) are at the heart of modern electronics, which rely heavily on the state-of-the-art semiconductor manufacturing technology. The key to pushing forward semiconductor technology is IC feature-size miniaturization. However, this brings ever-increasing design complexities and manufacturing challenges to the $340 billion semiconductor industry. The manufacturing of two-dimensional layout on high-density metal layers depends on complex design-for-manufacturing techniques and sophisticated empirical optimizations, which introduces huge amounts of turnaround time and yield loss in advanced technology nodes. Our study reveals that unidirectional layout design can significantly reduce the manufacturing complexities and improve the yield, which is becoming increasingly adopted in semiconductor industry [61, 89]. The lithography printing of unidirectional layout can be tightly controlled using advanced patterning techniques, such as self-aligned double and quadruple patterning. Despite the manufacturing benefits, unidirectional layout leads to more restrictive solution space and brings significant impacts on the IC design automation ow for routing closure. Notably, unidirectional routing limits the standard cell pin accessibility, which further exacerbates the resource competitions during routing. Moreover, for post-routing optimization, traditional redundant-via insertion has become obsolete under unidirectional routing style, which makes the yield enhancement task extremely challenging. Regardless of complex multiple patterning and design-for-manufacturing approaches, mask optimization through resolution enhancement techniques remains as the key strategy to improve the yield of the semiconductor manufacturing processes. Among them, Sub-Resolution Assist Feature (SRAF) generation is a very important method to improve lithographic process windows. Model-based SRAF generation has been widely used to achieve high accuracy but it is time-consuming and hard to obtain consistent SRAFs. This dissertation proposes novel CAD algorithms and methodologies for standard cell optimization and physical design in advanced technology nodes, which ultimately reduces the design cycle and manufacturing cost of IC design. First, a standard cell pin access optimization engine is proposed to evaluate the pin accessibility of a given standard cell library. We further propose novel pin access planning techniques and concurrent pin access optimizations to efficiently resolve the routing resource competitions, which generates much better routing solutions than state-of-the-art, manufacturing-friendly routers. To systematically improve the manufacturing yield in the post-routing stage, a global optimization engine has been introduced for redundant local-loop insertion considering advanced manufacturing constraints. Finally, we propose the first machine learning-based framework for fast yet consistent SRAF generation with the high quality of results.Electrical and Computer Engineerin

Resolution Enhancement Techniques (RET) for Immersion Lithography

Ph.DDOCTOR OF PHILOSOPH

Etude de la modification de la source dans l'utilisation de la méthode de co-optimisation source masque en lithographie optique : mise en oeuvre et applications

Conducted between December 2009 and December 2012 within the RET (resolution enhancement technology) team at STMicroelectronics Crolles and in partnership with Saint-Etienne laboratory Hubert Curien of the University of Lyon, this thesis entitled "Impact of changing the source while using the source mask optimization technique within optical lithography, and application to 20 nm technology node. ". In this thesis, Alleaume Clovis studied the optimization of the source used in optical lithography, technique usually called SMO (for source mask optimization) and applied the technique to the industry through several problems. The first part of the manuscript describe the optical lithography generalities, in order to allow a better understanding of the issues and the techniques used in this study. Indeed, to allow optical lithography to continue the miniaturization of microelectronic components, it is necessary to optimize many aspects of the lithography. The shape of the light source used is no exception to this rule and the use of extended sources, off-axis and more or less complex now enables the production of advanced technologies. The second part will then focus on the source modification and optimization. In a first step, the diffraction theory will be examined to demonstrate the theoretical interest of the thesis, and to allow a better understanding of the problem. Simulations and SEM measurements will be presented to show the effectiveness of SMO method. As this study gave birth to several innovative source optimization techniques, they will be presented. Thus, the method of internal SMO based on the phenomenon of diffraction and created during this thesis will be presented and the results would be studied. The application of the source optimization to industrial problems will also be presented through different applications. Finally, a legacy of knowledge will be done by presenting the different tools developed during this thesis. A third part will deal with the study of tool which generate the source inside the scanner allowing the use of optimized and complex sources. The thesis has given rise to a new source decomposition technique using Zernike polynomial. It will be used in this study to model the degradation of a source, and for correlating the impact of a source modification due to SMO technique on the empirical model stability. The study of sources has been implemented according to industrial aspect to monitor the scanner with a quick method. In addition to the Zernike decomposition method, simulations can be used to complete this study. The forth chapter of this study will talk about this implementation. Finally, the last part of the study will talk about the co-optimization of the source with several elements, such as the mask OPC and the final shape of the desired pattern. Indeed, if the initial shape of the desired pattern plays an important role in defining the source, it is possible to modify the latter design shape, as well as the shape of the mask in order to optimize both the source and the target shape. These changes will be discussed in the last chapterRéalisée entre décembre 2009 et décembre 2012 au sein de STMicroelectronics Crolles dans l’équipe RET (résolution enhancement techniques), et en partenariat avec le laboratoire Hubert Curien Saint Etienne de l’université de Lyon, cette thèse s’intitule "Impact de la modification de la source dans l’utilisation de la méthode de cooptimisation masque source en lithographie optique, et application au nœud technologique 20 nm". Durant cette étude, nous avons pu étudier la technique d’optimisation de la source optique en lithographie, appelée généralement SMO afin de l’appliquer aux problématiques de l’industrie. Une première partie du manuscrit traitant de la lithographie optique permettra de mieux comprendre les problématiques liées à cette étude, en présentant les techniques utilisées. En effet, afin de permettre à la lithographie optique de continuer la miniaturisation des composants de microélectronique, il est nécessaire d’optimiser au maximum de nombreux éléments de la lithographie. La forme de la source optique utilisée n’échappe pas à cette règle et l’utilisation de sources étendues, hors axe et plus ou moins complexe permet aujourd’hui la production des technologies de pointes. Une seconde partie s’attardera plus sur l’optimisation de la source à proprement parler. Dans un premier temps, la théorie de la diffraction sera étudiée afin de permettre une meilleure compréhension du problème. Des simulations et des mesures SEM ou microscope électronique à balayage seront présentées pour montrer l’efficacité de la méthode SMO, de l’anglais "Source Mask Optimization". Cette étude donnant lieu au développement de nouvelles méthodes rapides et innovantes d’optimisation de la source, l’étude prendra soin de présenter des résultats obtenus dans le cadre de cette thèse. Ainsi, la méthode de SMO interne basée sur le phénomène de diffraction et créée durant cette thèse sera présentée dans cette étude et les résultats en découlant seront étudiés. L’application de l’optimisation de la source à des problématiques industrielles sera également présentée à travers différentes applications des solutions proposées. Finalement, un legs de connaissance nécessaire sera effectué par la présentation des différents outils développés durant cette thèse. Une troisième partie concernera l’étude de l’outil Flexray permettant la génération des sources optimisées. La thèse ayant donné lieu à une nouvelle technique de décomposition de la source en polynôme de Zernike, cette techniques sera présentée ici. Elle sera ensuite utilisée pour modéliser la dégradation d’une source, ainsi que pour corréler la différence de source avec la divergence du modèle empirique de simulation. L’étude des sources a été mise en place suivant un aspect industrielle, afin de contrôler l’évolution du scanner de façon rapide. De plus, des simulations peuvent être utilisées pour compléter cette étude. Finalement, une dernière partie traitera de la cooptimisation entre la source et différents éléments tels que le masque et la forme final du motif souhaité. En effet, si la forme initiale du motif souhaité joue un rôle important dans la définition de la source, il est possible de modifier cette dernière, ainsi que la forme du masque en lui appliquant un OPC afin d’obtenir de meilleurs résultats. Ces modifications seront étudiées durant le dernier chapitr