Analysis and Survey of FPGA Based PROFIBUS Board

Fieldbus system has been established as a communication network, used to connect field devices such as sensors, transduser,controller,man machine interface.Currently a large number of global fieldbus standards are available for consumers.Citation of different types of field bus present an analytical review of various fieldbus systemthat how to gather the data from various equipment distributed far away from each other in the field with reduced wiring and cabling requirement, those are the basic components of communication system. This work also discuss about FPGA based PROFIBUS communication board. It proposes the alternative solution to complexity of communication system and devise it more reliable, high integral and transmission efficient

Design Solutions For Modular Satellite Architectures

The cost-effective access to space envisaged by ESA would open a wide range of new opportunities and markets, but is still many years ahead. There is still a lack of devices, circuits, systems which make possible to develop satellites, ground stations and related services at costs compatible with the budget of academic institutions and small and medium enterprises (SMEs). As soon as the development time and cost of small satellites will fall below a certain threshold (e.g. 100,000 to 500,000 €), appropriate business models will likely develop to ensure a cost-effective and pervasive access to space, and related infrastructures and services. These considerations spurred the activity described in this paper, which is aimed at: - proving the feasibility of low-cost satellites using COTS (Commercial Off The Shelf) devices. This is a new trend in the space industry, which is not yet fully exploited due to the belief that COTS devices are not reliable enough for this kind of applications; - developing a flight model of a flexible and reliable nano-satellite with less than 25,000€; - training students in the field of avionics space systems: the design here described is developed by a team including undergraduate students working towards their graduation work. The educational aspects include the development of specific new university courses; - developing expertise in the field of low-cost avionic systems, both internally (university staff) and externally (graduated students will bring their expertise in their future work activity); - gather and cluster expertise and resources available inside the university around a common high-tech project; - creating a working group composed of both University and SMEs devoted to the application of commercially available technology to space environment. The first step in this direction was the development of a small low cost nano-satellite, started in the year 2004: the name of this project was PiCPoT (Piccolo Cubo del Politecnico di Torino, Small Cube of Politecnico di Torino). The project was carried out by some departments of the Politecnico, in particular Electronics and Aerospace. The main goal of the project was to evaluate the feasibility of using COTS components in a space project in order to greatly reduce costs; the design exploited internal subsystems modularity to allow reuse and further cost reduction for future missions. Starting from the PiCPoT experience, in 2006 we began a new project called ARaMiS (Speretta et al., 2007) which is the Italian acronym for Modular Architecture for Satellites. This work describes how the architecture of the ARaMiS satellite has been obtained from the lesson learned from our former experience. Moreover we describe satellite operations, giving some details of the major subsystems. This work is composed of two parts. The first one describes the design methodology, solutions and techniques that we used to develop the PiCPoT satellite; it gives an overview of its operations, with some details of the major subsystems. Details on the specifications can also be found in (Del Corso et al., 2007; Passerone et al, 2008). The second part, indeed exploits the experience achieved during the PiCPoT development and describes a proposal for a low-cost modular architecture for satellite

Design of the user-friendly touch screen GUI and a physical connection to an existing simulation hardware device

Práce uvádí základní informace o průmyslové sběrnici AS-Interface a popisuje její funkce. Dále se zabývá rozšířením stávajícího FTZ AS-Interface Slave Simulátoru o dotykový display, který značně usnadní ovládání tohoto simulačního nástroje. Je zde nastíněn návrh a řešení uživatelského dotykového rozhraní k tomuto simulátoru s použitím Amulet LCD modulu STK 480272C. Vývoj tohoto rozhraní je proveden pomocí GEMstudia, softwaru firmy Amulet Technologies a grafických programů. Dále tato studie pojednává o softwarové úpravě FTZ AS-i Slave Smilulátoru. Jedná se o úpravu řídícího FPGA v jazyce VHDL zajišťující komunikaci s dotykovým displejem. Poslední kapitola se týká problematiky spojené s návrhem uživatelsky přívětivé aplikace.This master’s thesis deals with fundamental principles of the industrial bus AS- Interface as well as with an extension of the FTZ AS-Interface Slave Simulator by touch panel which makes it incomparably easy to control this device. Progress and solution of the touch communication interface for this Slave Simulator have been sketched out by using Amulet LCD module STK-480272C. The design of this communication interface has been created by GEMstudio, software of Amulet Technologies and graphics programs. Further this study deals with software adjustment of FTZ AS-i Slave Simulator. The modification of controlling FPGA in VHDL programming language has been described which ensures the communication with the touch screen. Last chapter deals with questions concerning a user-friendly design of the application.

Integrity Verification for SCADA Devices Using Bloom Filters and Deep Packet Inspection

In the past, SCADA networks were made secure through undocumented, proprietary protocols and isolation from other networks. Today, modern information technology (IT) solutions have provided a means to enhance remote access through use of the Internet. Unfortunately, opening SCADA networks to the Internet has provided routes of attack. Cyber attacks on these networks are becoming more common and can inflict considerable damage to critical infrastructure systems. Furthermore, devices on these networks can be infected with malware that causes them to falsify their responses to operators, concealing alternate operation or hiding alarm conditions. Considering their applications, securing these networks translates to improved physical security in the real world. Since modern IT solutions are impractical to deploy in the resource constrained SCADA networks, other solutions must be researched. This research evaluates an integrity verification system implemented on a Xilinx ML507 development board called the SIEVE system. The design incorporates Bloom filters and SCADA-specific intrusion detection techniques to speed identification of invalid commands and current sensing to investigate whether or not a device correctly carried out a given command. Results show that the SIEVE system is able to inspect and correctly identify 100% of network traffic at a 200 command per second frequency. Correct identification of valid MODBUS/TCP traffic begins to fail at 350 commands per second, introducing false positives. Tests of the Bloom filters show that they reduce the time necessary to process and log invalid MODBUS/TCP commands by 4.5% to 2328.06% depending on the number of operations performed by the command

Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments

RCE (Resource Constrained Environment) is known for its stringent hardware design requirements. With the rise of Internet of Things (IoT), low-complexity and low-area designs are becoming prominent in the face of complex security threats. Two low-complexity, low-area cryptographic processors based on the ultimate reduced instruction set computer (URISC) are created to provide security features for wireless visual sensor networks (WVSN) by using field-programmable gate array (FPGA) based visual processors typically used in RCEs. The first processor is the Two Instruction Set Computer (TISC) running the Skipjack cipher. To improve security, a Compact Instruction Set Architecture (CISA) processor running the full AES with modified S-Box was created. The modified S-Box achieved a gate count reduction of 23% with no functional compromise compared to Boyar’s. Using the Spartan-3L XC3S1500L-4-FG320 FPGA, the implementation of the TISC occupies 71 slices and 1 block RAM. The TISC achieved a throughput of 46.38 kbps at a stable 24MHz clock. The CISA which occupies 157 slices and 1 block RAM, achieved a throughput of 119.3 kbps at a stable 24MHz clock. The CISA processor is demonstrated in two main applications, the first in a multilevel, multi cipher architecture (MMA) with two modes of operation, (1) by selecting cipher programs (primitives) and sharing crypto-blocks, (2) by using simple authentication, key renewal schemes, and showing perceptual improvements over direct AES on images. The second application demonstrates the use of the CISA processor as part of a selective encryption architecture (SEA) in combination with the millions instructions per second set partitioning in hierarchical trees (MIPS SPIHT) visual processor. The SEA is implemented on a Celoxica RC203 Vertex XC2V3000 FPGA occupying 6251 slices and a visual sensor is used to capture real world images. Four images frames were captured from a camera sensor, compressed, selectively encrypted, and sent over to a PC environment for decryption. The final design emulates a working visual sensor, from on node processing and encryption to back-end data processing on a server computer

Design of a PC based wireless door security system

This project is developed by using Radio Frequency Identification (RFID) System, ATMEGA-32 Microcontroller and relay switching circuit to design a PC based Time attendance and Wireless door access system. The main objective of this project is to implement a time attendance system along with a door lock system for secure and reliable applications. The system gives all types of information regarding student registration, in-out track record, attendance details which can be used for future reference. In this project, both the hardware and software modules are integrated. The hardware module includes a Passive RFID reader, ATMEGA-32 microcontroller, Relay Switching circuit and LEDs. The advantage of using passive RFID is that it functions without a battery and passive tags are lighter and are less expensive than the active tags [4].The software module uses Microsoft visual studio 2008, which is designed in such a way that the hardware system is interfaced and controlled from the computer with a Graphical User Interface (GUI). The primary purpose of the project is to authenticate each user .The system enables user to check-in and check-out under fast, secure and convenient conditions. The system also includes door locking system which opens up when the user taps the tag on the RFID reader and the tag information is matched with the information already stored in database. The RFID reader along with ATMEGA-32 microcontroller controls the opening and closing of the door

Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments

RCE (Resource Constrained Environment) is known for its stringent hardware design requirements. With the rise of Internet of Things (IoT), low-complexity and low-area designs are becoming prominent in the face of complex security threats. Two low-complexity, low-area cryptographic processors based on the ultimate reduced instruction set computer (URISC) are created to provide security features for wireless visual sensor networks (WVSN) by using field-programmable gate array (FPGA) based visual processors typically used in RCEs. The first processor is the Two Instruction Set Computer (TISC) running the Skipjack cipher. To improve security, a Compact Instruction Set Architecture (CISA) processor running the full AES with modified S-Box was created. The modified S-Box achieved a gate count reduction of 23% with no functional compromise compared to Boyar’s. Using the Spartan-3L XC3S1500L-4-FG320 FPGA, the implementation of the TISC occupies 71 slices and 1 block RAM. The TISC achieved a throughput of 46.38 kbps at a stable 24MHz clock. The CISA which occupies 157 slices and 1 block RAM, achieved a throughput of 119.3 kbps at a stable 24MHz clock. The CISA processor is demonstrated in two main applications, the first in a multilevel, multi cipher architecture (MMA) with two modes of operation, (1) by selecting cipher programs (primitives) and sharing crypto-blocks, (2) by using simple authentication, key renewal schemes, and showing perceptual improvements over direct AES on images. The second application demonstrates the use of the CISA processor as part of a selective encryption architecture (SEA) in combination with the millions instructions per second set partitioning in hierarchical trees (MIPS SPIHT) visual processor. The SEA is implemented on a Celoxica RC203 Vertex XC2V3000 FPGA occupying 6251 slices and a visual sensor is used to capture real world images. Four images frames were captured from a camera sensor, compressed, selectively encrypted, and sent over to a PC environment for decryption. The final design emulates a working visual sensor, from on node processing and encryption to back-end data processing on a server computer