Design and implementation of OFDM signal processing on PSoC microcontroller

Article2013 International Conference on ICT Convergence (ICTC). 391-392 (2013)journal articl

Self-Scaling Evolution of Analog Computation Circuits

Energy and performance improvements of continuous-time analog-based computation for selected applications offer an avenue to continue improving the computational ability of tomorrow*s electronic devices at current technology scaling limits. However, analog computation is plagued by the difficulty of designing complex computational circuits, programmability, as well as the inherent lack of accuracy and precision when compared to digital implementations. In this thesis, evolutionary algorithm-based techniques are utilized within a reconfigurable analog fabric to realize an automated method of designing analog-based computational circuits while adapting the functional range to improve performance. A Self-Scaling Genetic Algorithm is proposed to adapt solutions to computationally-tractable ranges in hardware-constrained analog reconfigurable fabrics. It operates by utilizing a Particle Swarm Optimization (PSO) algorithm that operates synergistically with a Genetic Algorithm (GA) to adaptively scale and translate the functional range of computational circuits composed of high-level or low-level Computational Analog Elements to improve performance and realize functionality otherwise unobtainable on the intrinsic platform. The technique is demonstrated by evolving square, square-root, cube, and cube-root analog computational circuits on the Cypress PSoC-5LP System-on-Chip. Results indicate that the Self-Scaling Genetic Algorithm improves our error metric on average 7.18-fold, up to 12.92-fold for computational circuits that produce outputs beyond device range. Results were also favorable compared to previous works, which utilized extrinsic evolution of circuits with much greater complexity than was possible on the PSoC-5LP

Application and Development of Embedded Systems with IoT Components: Aspect of Safety and Reliability

We will present the possibilities of application and development, especially in the field of embedded systems, its interaction with other IoT components, the security aspects of individual components, as well as the domain of their interaction. In embedded systems, we will present new technologies such as fuzzy logic, application possibilities in embedded systems, and machine learning, as application possibilities through the implementation of machine learning. Then we will describe some more examples of the application of fuzzy logic, the automatic control of certain functions in cameras, as well as the defuzzification process, and the possibility of application in security cameras. In embedded systems, we will present the basic aspects of optimization and security, both in everyday applications and in interaction with other components of IoT technologies. The paper shows how security, reliability, and cost estimates affect the implementation phases and the final use of embedded systems, through examples of their application in industry. Security and data protection is shown through the construction of the mentioned devices, their application, but also different encryption methods, permissions, security devices at the network level, as well as implemented IoT technologies. Application examples are focused on the real segment, both in the field of transport, multimedia, design, and in the field of industrial application possibilities

Embedded electronic systems driven by run-time reconfigurable hardware

Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria

A Comparative study of Wireless Star Networks Implemented with Current Wireless Protocols

Wireless communication is one of the most advanced technological developments of this era. Wireless technology enables both short-range and long-range services. Today, there are several different wireless communication technologies in existence. Each has its characteristics different from another one. This thesis will implement three short-range wireless technologies in star connection and compare the performance in the wireless network. For this thesis, the performance of three different RF protocols - a proprietary packet protocol called Enhanced ShockBurst in nRF24L01+, Bluetooth Low Energy, and a special Wi- Fi protocol ESP-Now was compared. The general concept was to establish a star network for these protocols consisting of each module as a central hub while the others as end nodes, where all modules were configured as transceivers. The wireless star network for the proprietary radio frequency protocol Enhanced ShockBurst Feature was implemented using a transceiver device built by a Norwegian company Nordic Systems called the nRF24L01+. Similar wireless networks were also implemented for ESP-Now and BLE in an ESP32 development board. ESPNow is a proprietary radio frequency protocol developed by a Chinese company called Espressif that allows multiple devices to connect over 2.4 GHz channels using elements of a Wi-Fi protocol without requiring a router to form a network, while Bluetooth Low Energy is a wireless personal network designed by the Bluetooth Special Interest Group (Bluetooth SIG). Different performance metrics such as throughput (kbps), range (ft), current consumption (mA) and network routing recovery time (s) were measured in the network. From the implementations tested, it was found that the nRF24L01+ has maximum throughput when transmitting large payloads (344% higher than ESP-Now in 32 bytes payload size, BLE throughput was 50.50 bps in 32 bytes payload size), least current consumption (ESP-Now consumes 714% more current and BLE consumes 409.7% more current), and shortest network recovery time (nRF24L01+ took 335us, ESP-Now took 31ms and BLE took 1.3s on average), while the Wi-Fi based ESP-Now has a maximum range (30.53% better than BLE and 120% better than nRF24L01+)

Doctor of Philosophy

dissertationLow-cost wireless embedded systems can make radio channel measurements for the purposes of radio localization, synchronization, and breathing monitoring. Most of those systems measure the radio channel via the received signal strength indicator (RSSI), which is widely available on inexpensive radio transceivers. However, the use of standard RSSI imposes multiple limitations on the accuracy and reliability of such systems; moreover, higher accuracy is only accessible with very high-cost systems, both in bandwidth and device costs. On the other hand, wireless devices also rely on synchronized notion of time to coordinate tasks (transmit, receive, sleep, etc.), especially in time-based localization systems. Existing solutions use multiple message exchanges to estimate time offset and clock skew, which further increases channel utilization. In this dissertation, the design of the systems that use RSSI for device-free localization, device-based localization, and breathing monitoring applications are evaluated. Next, the design and evaluation of novel wireless embedded systems are introduced to enable more fine-grained radio signal measurements to the application. I design and study the effect of increasing the resolution of RSSI beyond the typical 1 dB step size, which is the current standard, with a couple of example applications: breathing monitoring and gesture recognition. Lastly, the Stitch architecture is then proposed to allow the frequency and time synchronization of multiple nodes' clocks. The prototype platform, Chronos, implements radio frequency synchronization (RFS), which accesses complex baseband samples from a low-power low-cost narrowband radio, estimates the carrier frequency offset, and iteratively drives the difference between two nodes' main local oscillators (LO) to less than 3 parts per billion (ppb). An optimized time synchronization and ranging protocols (EffToF) is designed and implemented to achieve the same timing accuracy as the state-of-the-art but with 59% less utilization of the UWB channel. Based on this dissertation, I could foresee Stitch and RFS further improving the robustness of communications infrastructure to GPS jamming, allow exploration of applications such as distributed beamforming and MIMO, and enable new highly-synchronous wireless sensing and actuation systems

Emerging Communications for Wireless Sensor Networks

Wireless sensor networks are deployed in a rapidly increasing number of arenas, with uses ranging from healthcare monitoring to industrial and environmental safety, as well as new ubiquitous computing devices that are becoming ever more pervasive in our interconnected society. This book presents a range of exciting developments in software communication technologies including some novel applications, such as in high altitude systems, ground heat exchangers and body sensor networks. Authors from leading institutions on four continents present their latest findings in the spirit of exchanging information and stimulating discussion in the WSN community worldwide

Diseño de arquitecturas eficientes basadas en dispositivos lógicos programables para técnicas de acceso al medio en comunicaciones PLC

En el trabajo propuesto en esta tesis se han estudiado, analizado y desarrollado nuevas arquitecturas para la implementación de técnicas de acceso al medio en comunicaciones PLC de banda ancha. Estas arquitecturas se han incluido como periféricos avanzados en un sistema SoC general basado en FPGAs que integra un microprocesador soft encargado de realizar la supervisión del sistema y la gestión de las transferencias de datos. Además, la arquitectura SoC general dispone de un módulo DMA que asegura el flujo de datos necesario para cada técnica de acceso al medio, permitiendo que todo el sistema opere en tiempo real, atendiendo a los requisitos del estándar de PLC de banda ancha. Para la definición de las distintas arquitecturas, se ha realizado un exhaustivo estudio de las técnicas de acceso al medio consideradas. Dentro de este estudio se ha efectuado un análisis de distintos algoritmos para su implementación, evaluándose las opciones más idóneas en cada caso. El análisis de distintas alternativas ha permitido obtener una arquitectura con un bajo consumo de recursos y que a su vez disponga de un tiempo de cómputo que permita la implementación en tiempo real. Esto se ha conseguido con el ratio de paralelismo, el cual ha permitido una reutilización a lo largo del tiempo de los recursos implicados, obteniéndose un compromiso entre tiempo de procesamiento y recursos empleados. Asimismo, dado que las arquitecturas se van a implantar sobre un dispositivo FPGA, es necesario considerar en todo este estudio el efecto de la precisión finita, ya que es determinante a la hora de obtener unas prestaciones adecuadas. Para ello, se ha tenido en especial consideración el dispositivo en el que se iba a realizar la implementación, utilizando el ancho de palabra máximo de las celdas aritméticas y de las memorias disponibles. Para la comprobación de la calidad de las arquitecturas diseñadas se han desarrollado modelos de simulación en coma flotante y en coma fija. La utilización de modelos de simulación permite realizar análisis cuantitativo del efecto de la precisión finita y a su vez comprobar que la implementación desarrollada es correcta. Tanto los modelos de simulación, como las posteriores pruebas experimentales, han sido evaluados en distintas escenarios prácticos, permitiendo una verificación precisa de los datos obtenidos y su corroboración con los resultados simulados. Los escenarios considerados han tenido en cuenta distintos tipos de canales de transmisión, incrementando el nivel de ruido y atenuación gradualmente. En el primer caso se ha empleado un canal ideal, que ha permitido realizar un estudio del efecto de la precisión finita sobre las arquitecturas propuestas. En el segundo caso se ha empleado un cable SMA como canal de transmisión. El cable SMA presenta una buena respuesta en frecuencia y por tanto se puede comparar la calidad de las arquitecturas en un sistema de transmisión completo, cuyo canal se aproxima al ideal. Por último, el tercer caso introduce un canal más agresivo formado por un cable eléctrico de doce metros. Con este canal se ha realizado una estimación del comportamiento de la técnica de acceso al medio en un canal similar al real sin el empleo de ningún módulo de estimación e igualación de canal