Design and Implementation of a Low‐Power Wireless Respiration Monitoring Sensor

Wireless devices for monitoring of respiration activities can play a major role in advancing modern home-based health care applications. Existing methods for respiration monitoring require special algorithms and high precision filters to eliminate noise and other motion artifacts. These necessitate additional power consuming circuitry for further signal conditioning. This dissertation is particularly focused on a novel approach of respiration monitoring based on a PVDF-based pyroelectric transducer. Low-power, low-noise, and fully integrated charge amplifiers are designed to serve as the front-end amplifier of the sensor to efficiently convert the charge generated by the transducer into a proportional voltage signal. To transmit the respiration data wirelessly, a lowpower transmitter design is crucial. This energy constraint motivates the exploration of the design of a duty-cycled transmitter, where the radio is designed to be turned off most of the time and turned on only for a short duration of time. Due to its inherent duty-cycled nature, impulse radio ultra-wideband (IR-UWB) transmitter is an ideal candidate for the implementation of a duty-cycled radio. To achieve better energy efficiency and longer battery lifetime a low-power low-complexity OOK (on-off keying) based impulse radio ultra-wideband (IR-UWB) transmitter is designed and implemented using standard CMOS process. Initial simulation and test results exhibit a promising advancement towards the development of an energy-efficient wireless sensor for monitoring of respiration activities

DESIGN OF A FOUR STAGES VCO USING A NOVEL DELAY CIRCUIT FOR OPERATION IN DISTRIBUTED BAND FREQUENCIES

The manuscript proposes a novel architecture of a delay cell that is implemented in 4-stage VCO which has the ability to operate in two distributed frequency bands. The operating frequency is chosen based on the principle of carrier mobility and the transistor resistance. The VCO uses dual delay input techniques to improve the frequency of operation. The design is implemented in Cadence 90nm GPDK CMOS technology and simulated results show that it is capable of operating in dual frequency bands of 55 MHz to 606 MHz and 857 MHz to 1049 MHz. At normal temperature (270) power consumption of the circuit is found to be 151μW at 606 MHz and 157μW at 1049 MHz respectively and consumes an area of 171.42µm2. The design shows good tradeoff between the parameters-operating frequency, phase noise and power consumption

A dual-mode Q-enhanced RF front-end filter for 5 GHz WLAN and UWB with NB interference rejection

The 5 GHz Wireless LAN (802.11a) is a popular standard for wireless indoor communications providing moderate range and speed. Combined with the emerging ultra Wideband standard (UWB) for short range and high speed communications, the two standards promise to fulfil all areas of wireless application needs. However, due to the overlapping of the two spectrums, the stronger 802.11a signals tend to interfere causing degradation to the UWB receiver. This presents one of the main technical challenges preventing the wide acceptance of UWB. The research work presented in this thesis is to propose a low cost RF receiver front-end filter topology that would resolve the narrowband (NB) interference to UWB receiver while being operable in both 802.11a mode and UWB mode. The goal of the dual mode filter design is to reduce cost and complexity by developing a fully integrated front-end filter. The filter design utilizes high Q passive devices and Q-enhancement technique to provide front-end channel-selection in NB mode and NB interference rejection in UWB mode. In the 802.11a NB mode, the filter has a tunable gain of 4 dB to 25 dB, NF of 8 dB and an IIP3 between -47 dBm and -18 dBm. The input impedance is matched at -16 dB. The frequency of operation can be tuned from 5.15 GHz to 5.35 GHz. In the UWB mode, the filter has a gain of 0 dB to 8 dB across 3.1 GHz to 9 GHz. The filter can reject the NB interference between 5.15 GHz to 5.35 GHz at up to 60 dB. The Q of the filter is tunable up to a 250 while consuming a maximum of 23.4 mW of power. The fully integrated dual mode filter occupies a die area of 1.1 mm2

Millimeter-scale RF Integrated Circuits and Antennas for Energy-efficient Wireless Sensor Nodes

Recently there has been increased demand for a millimeter-scale wireless sensor node for applications such as biomedical devices, defense, and surveillance. This form-factor is driven by a desire to be vanishingly small, injectable through a needle, or implantable through a minimally-invasive surgical procedure. Wireless communication is a necessity, but there are several challenges at the millimeter-scale wireless sensor node. One of the main challenges is external components like crystal reference and antenna become the bottleneck of realizing the mm-scale wireless sensor node device. A second challenge is power consumption of the electronics. At mm-scale, the micro-battery has limited capacity and small peak current. Moreover, the RF front-end circuits that operates at the highest frequency in the system will consume most of the power from the battery. Finally, as node volume reduces, there is a challenge of integrating the entire system together, in particular for the RF performance, because all components, including the battery and ICs, need to be placed in close proximity of the antenna. This research explores ways to implement low-power integrated circuits in an energy-constrained and volume constrained application. Three different prototypes are mainly conducted in the proposal. The first is a fully-encapsulated, autonomous, complete wireless sensor node with UWB transmitter in 10.6mm3 volume. It is the first time to demonstrate a full and stand-alone wireless sensing functionality with such a tiny integrated system. The second prototype is a low power GPS front-end receiver that supports burst-mode. A double super-heterodyne topology enables the reception of the three public GPS bands, L1, L2 and L5 simultaneously. The third prototype is an integrated rectangular slot loop antenna in a standard 0.13-μm BiCMOS technology. The antenna is efficiently designed to cover the bandwidth at 60 GHz band and easily satisfy the metal density rules and can be integrated with other circuitry in a standard process.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/143972/1/hskims_1.pd

The Design of Low Power Ultra-Wideband Transceiver

Ph.DDOCTOR OF PHILOSOPH

Microelectromechanical Systems for Wireless Radio Front-ends and Integrated Frequency References.

Microelectromechanical systems (MEMS) have great potential in realizing chip-scale integrated devices for energy-efficient analog spectrum processing. This thesis presents the development of a new class of MEMS resonators and filters integrated with CMOS readout circuits for RF front-ends and integrated timing applications. Circuit-level innovations coupled with new device designs allowed for realizing integrated systems with improved performance compared to standalone devices reported in the literature. The thesis is comprised of two major parts. The first part of the thesis is focused on developing integrated MEMS timing devices. Fused silica is explored as a new structural material for fabricating high-Q vibrating micromechanical resonators. A piezoelectric-on-silica MEMS resonator is demonstrated with a high Q of more than 20,000 and good electromechanical coupling. A low phase noise CMOS reference oscillator is implemented using the MEMS resonator as a mechanical frequency reference. Temperature-stable operation of the MEMS oscillator is realized by ovenizing the platform using an integrated heater. In an alternative scheme, the intrinsic temperature sensitivity of MEMS resonators is utilized for temperature sensing, and active compensation for MEMS oscillators is realized by oven-control using a phase-locked loop (PLL). CMOS circuits are implemented for realizing the PLL-based low-power oven-control system. The active compensation technique realizes a MEMS oscillator with an overall frequency drift within +/- 4 ppm across -40 to 70 °C, without the need for calibration. The CMOS PLL circuits for oven-control is demonstrated with near-zero phase noise invasion on the MEMS oscillators. The properties of PLL-based compensation for realizing ultra-stable MEMS frequency references are studied. In the second part of the thesis, RF MEMS devices, including tunable capacitors, high-Q inductors, and ohmic switches, are fabricated using a surface micromachined integrated passive device (IPD) process. Using this process, an integrated ultra-wideband (UWB) filter has been demonstrated, showing low loss and a small form factor. To further address the issue of narrow in-band interferences in UWB communication, a tunable MEMS bandstop filter is integrated with the bandpass filter with more than an octave frequency tuning range. The bandstop filter can be optionally switched off by employing MEMS ohmic switches co-integrated on the same chip.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/109069/1/zzwu_1.pd

Design exploration and measurement benchmark of integrated-circuits based on graphene field-effect-transistors : towards wireless nanotransceivers

This doctoral thesis approaches the design requirements for future high / ultra-high data rate (from 100 Mbps to 100 Gbps) nanotransceivers (nanoTRx) applied to wireless nanonetworks which imply short/ultra-short distance ranges (3 cm ¿ 3 m). It explores graphene field-effect-transistors (GFET), by simulation against measurement benchmarks, as a potential solution for implementing large-signal high-frequency circuits, by virtue of graphene¿s one-atom thickness and high carrier-mobility extraordinary properties. Finally, the thesis discusses the challenges faced by GFETs, such as zero-bandgap and high metal-graphene contact-resistance, to be able to propose improvements for achieving the initial proposed goals. Chemical-Vapour-Deposition (CVD) GFET fabrication is considered, which is very promising for large-scale manufacturing (CMOS process compatible), and for that fast-computing large-signal compact modeling for complex circuit design is analysed in depth and optimized, and consequently a set of diverse large-signal static and dynamic GFET circuits are simulated and benchmarked against available measurements assessing the accuracy of the proposed models and deriving scaling prospects. An optimization of the current-to-voltage (I-V) characteristic of a GFET compact model, based upon drift-diffusion carrier transport, is presented. The improved accuracy at the Dirac point extends the model usability for GFETs when scaling parameters such as voltage supply (Vdd), gate length (L), dielectric thickness (tox) and carrier mobility (¿) for large-signal design exploration in circuits. The model accuracy is demonstrated through parameters fitting to measurements taken from CVD GFETs fabricated in the University of Siegen and Technical University of Milan. The script has been written in a standard behavioural language (Verilog-A), and extensively run in a commercial analog circuit simulator (Cadence environment) demonstrating its robustness. Besides a simple capacitance-to-voltage model (C-V), a small-signal parasitic capacitance model fitted to dynamic measurements for self-aligned CVD GFETs available in the literature is added, enabling to forecast maximum-frequency-of-oscillation (fmax) trends for future scaling. A design-oriented characterization of complementary inverter circuits (INV) based on GFETs is presented as well. Our proposed compact model is benchmarked at the circuit level against another compact model based on a virtual-source approach. Furthermore, a benchmark between simulations and measurements of already fabricated CVD GFET INVs is performed, and performance trends when scaling are derived. The same process is repeated for a more complex circuit, namely GFET ring-oscillators (RO). The transient regime simulations yield performance metrics in terms of oscillation frequency (fosc) and dynamic voltage range (¿Vosc), and consequently, against these metrics, a comprehensive design space exploration covering as input design variables parameters as tox, L, and Vdd is carried out. Being aware of the lack of voltage amplification shown by existing GFETs, the design exploration of a cascode amplifier (CAS) targeted to increase voltage gain (Av) by decreasing its output conductance (go) is presented. GFET CAS are simulated to provide design guidelines, they are accordingly fabricated and consequently measured. Performance metrics are provided in terms of go, transconductance (gm) and hence Av. Against these metrics, a quantitative comparison between CAS and GFETs is performed and conclusions are derived. Finally, conclusions on GFETs suitability for future nanoTRX are elaborated. The derived publications come from international collaborations with the Royal Institute of Technology (KTH) in Sweden from 2012 to 2014, and the University of Siegen in Germany from 2014 to 2016.Esta tesis doctoral trata de identificar los requisitos de diseño para nano-ransceptores (nanoTRx) con datos de alta velocidad (de 100 Mbps a 100 Gbps) aplicados a nano-redes inal ámbricas que implican rangos de alcance cortos u ultra-cortos (3 cm - 3 m ); explora FETs de grafeno (GFET), mediante simulaciones y mediciones, como una solución potencial para la implementación de circuitos de alta frecuencia de gran señal, gracias a las extraordinarias propiedades del grafeno como su espesor de un solo átomo y sus portadores de alta movilidad; y finalmente, se discuten los desafíos a los que se enfrentan los GFETs, como la falta de banda prohibida y la alta resistencia de contacto, para lograr proponer alternativas y poder alcanzar los objetivos iniciales propuestos. Las publicaciones derivadas provienen de Colaboraciones internacionales con el KTH en Suecia de 2012 a 2014, y la UniSiegen en Alemania de 2014 a 2016. Se introducen la técnica CVD como un proceso de fabricación de GFETs a gran escala, compatible con tecnología CMOS, muy prometedor; y el modelado compacto de gran señal y computación veloz para el diseño de circuitos complejos es optimizados y analizado en profundidad, Consecuentemente circuitos de gran señal (estáticos y dinámicos) basados en GFET son simulados y comparados con las mediciones disponibles para evaluar la precisi ón de los modelos propuestos y derivar prospecciones de escalado. Se propone una optimización de la característica corriente-voltaje (I-V) de un modelo compacto GFET, basado en el transporte de portadores difusi ón-deriva. La precisión mejorada en el punto de Dirac extiende la usabilidad del modelo para GFETs cuando se dimensionan parámetros para la exploración en diseños de circuitos de gran señal, tales como el voltaje de alimentación (Vdd), la longitud de puerta (L), el espesor diel éctrico (tOX) y la movilidad de portadores (U). La precisión del modelo se demuestra a través de parámetros que se ajustan a mediciones tomadas a partir de CVD GFETs fabricados en la UniSiegen y en el PoliMi. El programa se ha escrito en Verilog-A y se ejecuta extensivamente en un simulador de circuitos anal ógico comercial donde se demuestra su robustez. Además, se lleva a cabo la parametrización de un modelo capacidad-voltaje (C-V) que se ajusta a las mediciones de alta frecuencia de CVD GFETs disponibles en la literatura científica, lo que permite la predicción de la fMAX para el escalado de futuros GFETs. También se presenta una caracterización orientada al diseño de circuitos inversores complementarios (INV) basados en GFETs. Nuestro modelo compacto propuesto se compara a nivel de circuito con otro modelo compacto basado en fuentevirtual. A continuación, se lleva a cabo una comparación a nivel circuito entre las simulaciones y las medidas de INVs ya fabricados basados en CVD GFET, y se obtienen las tendencias de comportamiento al escalarlos. Se repite el mismo proceso para un circuito más complejo, los llamados osciladores-en-anillo GFET (RO). Las simulaciones basadas en transitorios producen métricas de rendimiento en términos de frecuencia de oscilación (fosc) y rango dinámico de voltaje (Vosc), por lo tanto, contra estas métricas, se lleva a cabo una exploración exhaustiva de diseño que abarca Parámetros de variables de diseño como tOX, L y Vdd. Al ser conscientes de la falta de amplificación de voltaje mostrada por los GFETs existentes, se presenta la exploración de diseño de un amplificador cascodo (CAS) diseñado para incrementar la amplificación de voltaje (Av) disminuyendo su conductancia de salida (go). Los GFET CAS son simulados para proporcionar guías de diseño, luego fabricadas y finalmente medidas. Se proporcionan métricas de rendimiento en términos de go, gm, y consecuentemente Av. Frente a estas métricas, se realiza una comparación cuantitativa entre CAS y GFETs y se derivan las conclusiones. Finalmente, se elaboran las conclusiones sobre la idoneidad de los GFET para futuros nanoTR

A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing

This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.Ph.D.Committee Chair: Kim, Jongman; Committee Member: Kang, Sung Ha; Committee Member: Lee, Chang-Ho; Committee Member: Mukhopadhyay, Saibal; Committee Member: Tentzeris, Emmanouil

Ultra-Low-Power Uwb Impulse Radio Design: Architecture, Circuits, And Applications

Recent advances in home healthcare, environmental sensing, and low power computing have created a need for wireless communication at very low power for low data rate applications. Due to higher energy/bit requirements at lower data -rate, achieving power levels low enough to enable long battery lifetime (~10 years) or power-harvesting supplies have not been possible with traditional approaches. Dutycycled radios have often been proposed in literature as a solution for such applications due to their ability to shut off the static power consumption at low data rates. While earlier radio nodes for such systems have been proposed based on a type of sleepwake scheduling, such implementations are still power hungry due to large synchronization uncertainty (~1[MICRO SIGN]s). In this dissertation, we utilize impulsive signaling and a pulse-coupled oscillator (PCO) based synchronization scheme to facilitate a globally synchronized wireless network. We have modeled this network over a widely varying parameter space and found that it is capable of reducing system cost as well as providing scalability in wireless sensor networks. Based on this scheme, we implemented an FCC compliant, 3-5GHz, timemultiplexed, dual-band UWB impulse radio transceiver, measured to consume only 20[MICRO SIGN]W when the nodes are synchronized for peer-peer communication. At the system level the design was measured to consume 86[MICRO SIGN]W of power, while facilitating multi- hop communication. Simple pulse-shaping circuitry ensures spectral efficiency, FCC compliance and ~30dB band-isolation. Similarly, the band-switchable, ~2ns turn-on receiver implements a non-coherent pulse detection scheme that facilitates low power consumption with -87dBm sensitivity at 100Kbps. Once synchronized the nodes exchange information while duty-cycling, and can use any type of high level network protocols utilized in packet based communication. For robust network performance, a localized synchronization detection scheme based on relative timing and statistics of the PCO firing and the timing pulses ("sync") is reported. No active hand-shaking is required for nodes to detect synchronization. A self-reinforcement scheme also helps maintain synchronization even in the presence of miss-detections. Finally we discuss unique ways to exploit properties of pulse coupled oscillator networks to realize novel low power event communication, prioritization, localization and immediate neighborhood validation for low power wireless sensor applications

Beamforming ultra-wideband transmitter

Master'sMASTER OF ENGINEERIN