OPTIMIZATION OF FPGA-BASED PROCESSOR ARCHITECTURE FOR SOBEL EDGE DETECTION OPERATOR

This dissertation introduces an optimized processor architecture for Sobel edge detection operator on field programmable gate arrays (FPGAs). The processor is optimized by the use of several optimization techniques that aim to increase the processor throughput and reduce the processor logic utilization and memory usage. FPGAs offer high levels of parallelism which is exploited by the processor to implement the parallel process of edge detection in order to increase the processor throughput and reduce the logic utilization. To achieve this, the proposed processor consists of several Sobel instances that are able to produce multiple output pixels in parallel. This parallelism enables data reuse within the processor block. Moreover, the processor gains performance with a factor equal to the number of instances contained in the processor block. The processor that consists of one row of Sobel instances exploits data reuse within one image line in the calculations of the horizontal gradient. Data reuse within one and multiple image lines is enabled by using a processor with multiple rows of Sobel instances which allow the reuse of both the horizontal and vertical gradients. By the application of the optimization techniques, the proposed Sobel processor is able to meet real-time performance constraints due to its high throughput even with a considerably low clock frequency. In addition, logic utilization of the processor is low compared to other Sobel processors when implemented on ALTERA Cyclone II DE2-70

Human behavioural analysis with self-organizing map for ambient assisted living

This paper presents a system for automatically classifying the resting location of a moving object in an indoor environment. The system uses an unsupervised neural network (Self Organising Feature Map) fully implemented on a low-cost, low-power automated home-based surveillance system, capable of monitoring activity level of elders living alone independently. The proposed system runs on an embedded platform with a specialised ceiling-mounted video sensor for intelligent activity monitoring. The system has the ability to learn resting locations, to measure overall activity levels and to detect specific events such as potential falls. First order motion information, including first order moving average smoothing, is generated from the 2D image coordinates (trajectories). A novel edge-based object detection algorithm capable of running at a reasonable speed on the embedded platform has been developed. The classification is dynamic and achieved in real-time. The dynamic classifier is achieved using a SOFM and a probabilistic model. Experimental results show less than 20% classification error, showing the robustness of our approach over others in literature with minimal power consumption. The head location of the subject is also estimated by a novel approach capable of running on any resource limited platform with power constraints

Software Defined Multi-Spectral Imaging for Arctic Sensor Networks

Availability of off-the-shelf infrared sensors combined with high definition visible cameras has made possible the construction of a Software Defined Multi-Spectral Imager (SDMSI) combining long-wave, near-infrared and visible imaging. The SDMSI requires a real-time embedded processor to fuse images and to create real-time depth maps for opportunistic uplink in sensor networks. Researchers at Embry Riddle Aeronautical University working with University of Alaska Anchorage at the Arctic Domain Awareness Center and the University of Colorado Boulder have built several versions of a low-cost drop-in-place SDMSI to test alternatives for power efficient image fusion. The SDMSI is intended for use in field applications including marine security, search and rescue operations and environmental surveys in the Arctic region. Based on Arctic marine sensor network mission goals, the team has designed the SDMSI to include features to rank images based on saliency and to provide on camera fusion and depth mapping. A major challenge has been the design of the camera computing system to operate within a 10 to 20 Watt power budget. This paper presents a power analysis of three options: 1) multi-core, 2) field programmable gate array with multi-core, and 3) graphics processing units with multi-core. For each test, power consumed for common fusion workloads has been measured at a range of frame rates and resolutions. Detailed analyses from our power efficiency comparison for workloads specific to stereo depth mapping and sensor fusion are summarized. Preliminary mission feasibility results from testing with off-the-shelf long-wave infrared and visible cameras in Alaska and Arizona are also summarized to demonstrate the value of the SDMSI for applications such as ice tracking, ocean color, soil moisture, animal and marine vessel detection and tracking. The goal is to select the most power efficient solution for the SDMSI for use on UAVs (Unoccupied Aerial Vehicles) and other drop-in-place installations in the Arctic. The prototype selected will be field tested in Alaska in the summer of 2016

IoT Based Image Processing Filters

Internet of things (IoT) becomes the backbone of the advanced countries and it has a real contribute to exchange the traditional style or way of practical life, even personal life into smart style, with (IoT) technology the life become more and more easy and professional. internet of things achieves various applications coordinate with sensors and standard protocols to apply what is called machine -to- machine connection (M2M), in this paper we will talk more about the concept of (M2M), the main component of internet of things and finally the common protocols that is used in network, in addition to that this work present an IOT operation with processing system using camera for capturing image and Xilinx system generator(XSG)models for designing  image processing algorithms and the result of  the processing is an image with black and white for edge detection and Thresholding models  and gray color image for gray enhancement model

An EMG-based patient monitoring system using Zynq SoC device

This thesis describes the design, development, and testing of an EMG-based patient monitoring system using the Zynq device. Zynq is a system on chip device designed by Xilinx which consists of an ARM dual cortex-A9 processor as well as an FPGA integrated into one chip. This work also analyzes the performance of image-processing algorithms on this system and compares that performance to more traditional PC-based systems. Image processing algorithms, such as Sobel edge detection, dilation and erosion, could be used in conjunction with a camera for the patient monitoring purposes. These algorithms often perform sub-optimally on processors because of their high computation demand, thus they are excellent candidates for the hardware acceleration available on an FPGA. This analysis shows that the performance of these algorithms in hardware using the Zynq-based architecture perform about 1800 times faster than the MATLAB implementation and 40 times faster than the OpenCV implementation on the PC. Moreover, the power consumption of the Zynq device proved to be about six and five times less than PC-based implementation using MATLAB and OpenCV respectively. Thus, the Zynq-based patient monitoring system proved to be both higher performance and lower power than a processor-based system. Both factors, performance and power consumption, are crucial for patient monitoring because of the demand for mobility and battery-based systems

Heterogeneous computing systems for vision-based multi-robot tracking

Irwansyah A. Heterogeneous computing systems for vision-based multi-robot tracking. Bielefeld: Universität Bielefeld; 2017

Reification: A Process to Configure Java Realtime Processors

Real-time systems require stringent requirements both on the processor and the software application. The primary concern is speed and the predictability of execution times. In all real-time applications the developer must identify and calculate the worst case execution times (WCET) of their software. In almost all cases the processor design complexity impacts the analysis when calculating the WCET. Design features which impact this analysis include cache and instruction pipelining. With both cache and pipelining the time taken for a particular instruction can vary depending on cache and pipeline contents. When calculating the WCET the developer must ignore the speed advantages from these enhancements and use the normal instruction timings. This investigation is about a Java processor targeted to run within an FPGA environment (Java soft chip) supporting Java real-time applications. The investigation focuses on a simple processor design that allows simple analysis of WCET. The processor design has no cache and no instruction pipeline enhancements yet achieves higher performance than existing designs with these enhancements. The investigation centers on a process that translates Java byte codes and folds these translated codes into a modified Harvard Micro Controller (HMC). The modifications include better alignment with the application code and take advantage of the FPGA’s parallel capability. A prototyped ontology is used where the top level categories defined by Sowa are expanded to support the process. The proposed HMC and process are used to produce investigation results. Performance testing using the Sobel edge detection algorithm is used to compare the results with the only Java processor claiming real-time abilities

Machine Vision for intelligent Semi-Autonomous Transport (MV-iSAT)

AbstractThe primary focus was to develop a vision-based system suitable for the navigation and mapping of an indoor, single-floor environment. Devices incorporating an iSAT system could be used as ‘self-propelled’ shopping carts in high-end retail stores or as automated luggage routing systems in airports. The primary design feature of this system is its Field Programmable Gate Array (FPGA) core, chosen for its strengths in parallelism and pipelining. Image processing has been successfully demonstrated in real-time using FPGA hardware. Remote feedback and monitoring was broadcasted to a host computer via a local area network. Deadlines as short as 40ns have been met by a custom built memory-based arbitration scheme. It is hoped that the iSAT platform will provide the basis for future work on advanced FPGA-based machine-vision algorithms for mobile robotics

Embedded machine vision - a parallel architecture approach -

Master'sMASTER OF ENGINEERIN