On detection of OFDM signals for cognitive radio applications

As the requirement for wireless telecommunications services continues to grow, it has become increasingly important to ensure that the Radio Frequency (RF) spectrum is managed efficiently. As a result of the current spectrum allocation policy, it has been found that portions of RF spectrum belonging to licensed users are often severely underutilised, at particular times and geographical locations. Awareness of this problem has led to the development of Dynamic Spectrum Access (DSA) and Cognitive Radio (CR) as possible solutions. In one variation of the shared-use model for DSA, it is proposed that the inefficient use of licensed spectrum could be overcome by enabling unlicensed users to opportunistically access the spectrum when the licensed user is not transmitting. In order for an unlicensed device to make decisions, it must be aware of its own RF environment and, therefore, it has been proposed that DSA could been abled using CR. One approach that has be identified to allow the CR to gain information about its operating environment is spectrum sensing. An interesting solution that has been identified for spectrum sensing is cyclostationary detection. This property refers to the inherent periodic nature of the second order statistics of many communications signals. One of the most common modulation formats in use today is Orthogonal Frequency Division Multiplexing (OFDM), which exhibits cyclostationarity due to the addition of a Cyclic Prefix (CP). This thesis examines several statistical tests for cyclostationarity in OFDM signals that may be used for spectrum sensing in DSA and CR. In particular, focus is placed on statistical tests that rely on estimation of the Cyclic Autocorrelation Function (CAF). Based on splitting the CAF into two complex component functions, several new statistical tests are introduced and are shown to lead to an improvement in detection performance when compared to the existing algorithms. The performance of each new algorithm is assessed in Additive White Gaussian Noise (AWGN), impulsive noise and when subjected to impairments such as multipath fading and Carrier Frequency Offset (CFO). Finally, each algorithm is targeted for Field Programmable Gate Array (FPGA) implementation using a Xilinx 7 series device. In order to keep resource costs to a minimum, it is suggested that the new algorithms are implemented on the FPGA using hardware sharing, and a simple mathematical re-arrangement of certain tests statistics is proposed to circumvent a costly division operation.As the requirement for wireless telecommunications services continues to grow, it has become increasingly important to ensure that the Radio Frequency (RF) spectrum is managed efficiently. As a result of the current spectrum allocation policy, it has been found that portions of RF spectrum belonging to licensed users are often severely underutilised, at particular times and geographical locations. Awareness of this problem has led to the development of Dynamic Spectrum Access (DSA) and Cognitive Radio (CR) as possible solutions. In one variation of the shared-use model for DSA, it is proposed that the inefficient use of licensed spectrum could be overcome by enabling unlicensed users to opportunistically access the spectrum when the licensed user is not transmitting. In order for an unlicensed device to make decisions, it must be aware of its own RF environment and, therefore, it has been proposed that DSA could been abled using CR. One approach that has be identified to allow the CR to gain information about its operating environment is spectrum sensing. An interesting solution that has been identified for spectrum sensing is cyclostationary detection. This property refers to the inherent periodic nature of the second order statistics of many communications signals. One of the most common modulation formats in use today is Orthogonal Frequency Division Multiplexing (OFDM), which exhibits cyclostationarity due to the addition of a Cyclic Prefix (CP). This thesis examines several statistical tests for cyclostationarity in OFDM signals that may be used for spectrum sensing in DSA and CR. In particular, focus is placed on statistical tests that rely on estimation of the Cyclic Autocorrelation Function (CAF). Based on splitting the CAF into two complex component functions, several new statistical tests are introduced and are shown to lead to an improvement in detection performance when compared to the existing algorithms. The performance of each new algorithm is assessed in Additive White Gaussian Noise (AWGN), impulsive noise and when subjected to impairments such as multipath fading and Carrier Frequency Offset (CFO). Finally, each algorithm is targeted for Field Programmable Gate Array (FPGA) implementation using a Xilinx 7 series device. In order to keep resource costs to a minimum, it is suggested that the new algorithms are implemented on the FPGA using hardware sharing, and a simple mathematical re-arrangement of certain tests statistics is proposed to circumvent a costly division operation

Design and implementation of synchronization and AGC for OFDM-based WLAN receivers

An efficient implementation of several tasks at the receiver becomes crucial in OFDM-based high-speed WLAN systems, such as automatic gain control, time and frequency synchronization and offset tracking. This paper deals with fixed point constraints and accuracy requirements for implementation of those algorithms. Also, a complete set of thresholds for the practical implementation of time and frequency synchronization sub-blocks is obtained. Moreover, a technique to mitigate the remaining frequency offset after coarse acquisition is proposed, yielding a good trade-off between performance and complexity. Finally, we propose the implementation of a simple and effective automatic gain control procedure.This work has been partially funded by Spanish government with project TIC 2002-03498 (ORISE), Telefonica I+D by the contract nº 25756, and the Chamber of Madrid Community and European Social Fund by a grant to the first author

FPGA implementation of an OFDM-based WLAN receiver

This paper deals with the design and implementation on FPGA of a receiver for OFDM-based WLAN. The circuit is particularized for IEEE 802.11a/g standards. The system includes frame detection, time and frequency synchronization, demodulation, equalization and phase tracking. The algorithms to be implemented for each task are selected taking into account performance, hardware cost and latency. Also, a fixed point analysis is made for each algorithm. Our objective is to maintain the PER loss below 0.5 dB for a PER = 10 -2, 64-QAM and error correction. The whole system is composed of two main blocks (correlator and CORDIC) that are reused in different time intervals to perform all the necessary operations, so the required hardware resources are minimized. To verify it, the receiver is physically implemented and tested. © 2011 Elsevier B.V. All rights reserved.This work was supported by the Spanish Ministerio de Educacion y Ciencia under grant TEC2008-06787.Canet Subiela, MJ.; Valls Coquillat, J.; Almenar Terré, V.; Marín-Roig Ramón, J. (2012). FPGA implementation of an OFDM-based WLAN receiver. Microprocessors and Microsystems. 36(3):232-244. https://doi.org/10.1016/j.micpro.2011.11.004S23224436

Design and implementation of a downlink MC-CDMA receiver

Cette thèse présente une étude d'un système complet de transmission en liaison descendante utilisant la technologie multi-porteuse avec l'accès multiple par division de code (Multi-Carrier Code Division Multiple Access, MC-CDMA). L'étude inclut la synchronisation et l'estimation du canal pour un système MC-CDMA en liaison descendante ainsi que l'implémentation sur puce FPGA d'un récepteur MC-CDMA en liaison descendante en bande de base. Le MC-CDMA est une combinaison de la technique de multiplexage par fréquence orthogonale (Orthogonal Frequency Division Multiplexing, OFDM) et de l'accès multiple par répartition de code (CDMA), et ce dans le but d'intégrer les deux technologies. Le système MC-CDMA est conçu pour fonctionner à l'intérieur de la contrainte d'une bande de fréquence de 5 MHz pour les modèles de canaux intérieur/extérieur pédestre et véhiculaire tel que décrit par le "Third Genaration Partnership Project" (3GPP). La composante OFDM du système MC-CDMA a été simulée en utilisant le logiciel MATLAB dans le but d'obtenir des paramètres de base. Des codes orthogonaux à facteur d'étalement variable (OVSF) de longueur 8 ont été choisis comme codes d'étalement pour notre système MC-CDMA. Ceci permet de supporter des taux de transmission maximum jusquà 20.6 Mbps et 22.875 Mbps (données non codées, pleine charge de 8 utilisateurs) pour les canaux intérieur/extérieur pédestre et véhiculaire, respectivement. Une étude analytique des expressions de taux d'erreur binaire pour le MC-CDMA dans un canal multivoies de Rayleigh a été réalisée dans le but d'évaluer rapidement et de façon précise les performances. Des techniques d'estimation de canal basées sur les décisions antérieures ont été étudiées afin d'améliorer encore plus les performances de taux d'erreur binaire du système MC-CDMA en liaison descendante. L'estimateur de canal basé sur les décisions antérieures et utilisant le critère de l'erreur quadratique minimale linéaire avec une matrice' de corrélation du canal de taille 64 x 64 a été choisi comme étant un bon compromis entre la performance et la complexité pour une implementation sur puce FPGA. Une nouvelle séquence d'apprentissage a été conçue pour le récepteur dans la configuration intérieur/extérieur pédestre dans le but d'estimer de façon grossière le temps de synchronisation et le décalage fréquentiel fractionnaire de la porteuse dans le domaine du temps. Les estimations fines du temps de synchronisation et du décalage fréquentiel de la porteuse ont été effectués dans le domaine des fréquences à l'aide de sous-porteuses pilotes. Un récepteur en liaison descendante MC-CDMA complet pour le canal intérieur /extérieur pédestre avec les synchronisations en temps et en fréquence en boucle fermée a été simulé avant de procéder à l'implémentation matérielle. Le récepteur en liaison descendante en bande de base pour le canal intérieur/extérieur pédestre a été implémenté sur un système de développement fabriqué par la compagnie Nallatech et utilisant le circuit XtremeDSP de Xilinx. Un transmetteur compatible avec le système de réception a également été réalisé. Des tests fonctionnels du récepteur ont été effectués dans un environnement sans fil statique de laboratoire. Un environnement de test plus dynamique, incluant la mobilité du transmetteur, du récepteur ou des éléments dispersifs, aurait été souhaitable, mais n'a pu être réalisé étant donné les difficultés logistiques inhérentes. Les taux d'erreur binaire mesurés avec différents nombres d'usagers actifs et différentes modulations sont proches des simulations sur ordinateurs pour un canal avec bruit blanc gaussien additif

FPGA based implementation of IEEE 80211a physical layer

Ankara : The Department of Electrical and Electronics Engineering and the Institute of Engineering and Sciences of Bilkent University, 2010.Thesis (Master's) -- Bilkent University, 2010.Includes bibliographical references leaves 57-59.Orthogonal Frequency Division Multiplexing (OFDM) is a multicarrier transmission technique, in which a single bitstream is transmitted over a large number of closely-spaced orthogonal subcarriers. It has been adopted for several technologies, such as Wireless Local Area Networks (WLAN), Digital Audio and Terrestrial Television Broadcasting and Worldwide Interoperability for Microwave Access (WiMAX) systems. In this work, IEEE802.11a WLAN standard was implemented on Field Programmable Gate Array (FPGA) for being familiar with the implementation problems of OFDM systems. The algorithms that are used in the implementation were firstly built up in MATLAB environment and the performance of system was observed with a simulator developed for this purpose. The transmitter and receiver FPGA implementations, which support the transmission rates from 6 to 54 Mbps, were designed in Xilinx System Generator Toolbox for MATLAB Simulink environment. The modulation technique and the Forward Error Coding (FEC) rate used at the transmitter are automatically adjusted by the desired bitrate as BPSK, QPSK, 16QAM or 64QAM and 1/2, 2/3 or 3/4, respectively.The transceiver utilizes 5986 slices, 45 block RAMs and 73 multipliers of a Xilinx Virtex-4 sx35 chip corresponding to % 39 of the resources. In addition, the FPGA implementation of the transceiver was also tested by constructing a wireless link between two Lyrtech Software Defined Radio Development Kits and the bit error rate of the designed system was measured by performing a digital loop-back test under an Additive White Gaussian Noise (AWGN) channel.İnce, MustafaM.S