Field Programmable Gate Arrays (FPGAs) II

This Edited Volume Field Programmable Gate Arrays (FPGAs) II is a collection of reviewed and relevant research chapters, offering a comprehensive overview of recent developments in the field of Computer and Information Science. The book comprises single chapters authored by various researchers and edited by an expert active in the Computer and Information Science research area. All chapters are complete in itself but united under a common research study topic. This publication aims at providing a thorough overview of the latest research efforts by international authors on Computer and Information Science, and open new possible research paths for further novel developments

Application of Optimization Techniques to Spectrally Modulated, Spectrally Encoded Waveform Design

A design process is demonstrated for a coexistent scenario containing Spectrally Modulated, Spectrally Encoded (SMSE) and Direct Sequence Spread Spectrum (DSSS) signals. Coexistent SMSE-DSSS designs are addressed under both perfect and imperfect DSSS code tracking conditions using a non-coherent delay-lock loop (DLL). Under both conditions, the number of SMSE subcarriers and subcarrier spacing are the optimization variables of interest. For perfect DLL code tracking conditions, the GA and RSM optimization processes are considered independently with the objective function being end-to-end DSSS bit error rate. A hybrid GA-RSM optimization process is used under more realistic imperfect DLL code tracking conditions. In this case, optimization is accomplished using a correlation degradation metric with the GA process being first applied to generate a “coarse” solution followed by RSM processing which provides the final optimized solution. This work has successfully expanded the practical utility of a previously developed tool, the original SMSE framework, by demonstrating a more efficient, structured means for coexistent waveform design that replaces previous trial and error methods

Measuring the Phase Variation of a DOCSIS 3.1 Full Duplex Channel

Including a Full Duplex option into DOCSIS introduces several problems. One of the more troublesome issues is the presence of a strong self interference signal that leaks from the transmit side to the receive side of a cable node. This self interference is caused by echoes in the channel that translate the forward travelling transmit signals into a reverse travelling signal, as well as, by leakage from the hybrid coupler used to couple the upstream and downstream signals. To suppress this self interference an echo canceller is implemented to remove the unwanted interference from the received signal. Unfortunately with the high rates of data transmission used in modern day CATV networks the echo canceller needs tremendous precision. A major concern in the implementation of Full Duplex into DOCSIS is if the channels used are even very slightly time varying. The echos in such channels change with time and can be difficult for the echo canceller to track. Changes in the response of the channel cause the echo profile of the network to shift and the echo canceler to re-adapt to the new channel response. The issue with this changing response is that it is possible for the channel to change faster than the echo canceller can adapt, resulting in the interference becoming unacceptably high. Since the channel is a physical network of coaxial cables often exposed to the environment, its propagation properties can be affected by wind swaying pole mounted cables, or by rapid heating from the sun, or sudden shifts in the load of the network. With information on how the physical properties of the cable changes, the engineers designing the echo canceller can know how fast the canceller must adapt to changes and also have a better measure of how reliable its echo cancellation will be. In this thesis the stability of the echo profile of the channel is measured. It is shown that the property of the channel with the greatest potential to rapidly change and cause noise after echo cancellation is the phase response of the channel. Due to this, the approach of this thesis is to measure the fluctuations in the phase of the channel response of a CATV network constructed in the lab. To measure the fluctuations in the phase response of the channel, a PLL (Phase Locked Loop) based circuit is designed and built on an FPGA (Field Programmable Gate Array) and connected to a model of a simple CATV network. The PLL circuit used to measure the phase fluctuations of the channel is designed to be able to measure changes occurring faster than 0.1 Hz and with a power higher than $10^{-7} \: V^2$. The circuit is able to capture data from the channel over a period of 90 seconds. Using this phase variation measurement circuit a series of experiments were performed on a model CATV DOCSIS network. It was found that many physical disturbances to the network had the effect of rapidly shifting the phase response of the network. Heating the cables in the network was found to shift the phase response upwards of $20000\:\mu$radians. Flexing the cables in the network was found to have a peak phase variation of $8000\: \mu$radians with similar effects found from walking over cables. Overall, it was clear that physical effects on the network had the propensity to rapidly shift the network response. Any echo canceller that is designed in the future will have to consider these effects when reporting the cancellation that it is able to achieve

FPGA IMPLEMENTATION OF A REALTIME CYCLOSTATIONARY FEATURE DETECTOR FOR OFDM SIGNALS

The demand for wireless connectivity has prompted regulatory authorities in the United States to investigate spectrum sharing of the DSRC band with U-NII operators. However, DSRC operation has public safety implications, and moreover, time-critical requirements due to the vehicular nature of its application. The field of cognitive radio has identified several sensing techniques for the identification of licensed operators in a given band. This thesis explores cyclostationary detection techniques for primary users. A method will be identified for the detection of the 802.11p OFDM modulation used for DSRC communications. A test statistic will be given that is invariant to the signal noise covariance to allow simple and robust operation. Finally, the detection algorithm will be implemented in FPGA digital logic in order to demonstrate the methods ability to be employed in a commercial radio chipset with minimum resource requirements, yet still provide real-time detection

Implementing the SC-FDMA transmission technique using the GNURadio platform

Dissertação apresentada para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores, pela Universidade Nova de Lisboa, Faculdade de Ciências e TecnologiaFCT/MEC - (PTDC/EEA- TEL/120666/2010), MANY2COMWIN (EXPL/EEI-TEL/0969/2013) and ADIN (PTDC/EEI-TEL/2990/2012

Massive Access in Cell-Free Massive MIMO-Based Internet of Things: Cloud Computing and Edge Computing Paradigms

This paper studies massive access in cell-free massive multi-input multi-output (MIMO) based Internet of Things and solves the challenging active user detection (AUD) and channel estimation (CE) problems. For the uplink transmission, we propose an advanced frame structure design to reduce the access latency. Moreover, by considering the cooperation of all access points (APs), we investigate two processing paradigms at the receiver for massive access: cloud computing and edge computing. For cloud computing, all APs are connected to a centralized processing unit (CPU), and the signals received at all APs are centrally processed at the CPU. While for edge computing, the central processing is offloaded to part of APs equipped with distributed processing units, so that the AUD and CE can be performed in a distributed processing strategy. Furthermore, by leveraging the structured sparsity of the channel matrix, we develop a structured sparsity-based generalized approximated message passing (SS-GAMP) algorithm for reliable joint AUD and CE, where the quantization accuracy of the processed signals is taken into account. Based on the SS-GAMP algorithm, a successive interference cancellation-based AUD and CE scheme is further developed under two paradigms for reduced access latency. Simulation results validate the superiority of the proposed approach over the state-of-the-art baseline schemes. Besides, the results reveal that the edge computing can achieve the similar massive access performance as the cloud computing, and the edge computing is capable of alleviating the burden on CPU, having a faster access response, and supporting more flexible AP cooperation.Comment: 17 pages, 16 figures. The current version has been accepted by IEEE Journal on Selected Areas in Communications (JSAC) Special Issue on Massive Access for 5G and Beyon

FPGA implementation of an OFDM-based WLAN receiver

This paper deals with the design and implementation on FPGA of a receiver for OFDM-based WLAN. The circuit is particularized for IEEE 802.11a/g standards. The system includes frame detection, time and frequency synchronization, demodulation, equalization and phase tracking. The algorithms to be implemented for each task are selected taking into account performance, hardware cost and latency. Also, a fixed point analysis is made for each algorithm. Our objective is to maintain the PER loss below 0.5 dB for a PER = 10 -2, 64-QAM and error correction. The whole system is composed of two main blocks (correlator and CORDIC) that are reused in different time intervals to perform all the necessary operations, so the required hardware resources are minimized. To verify it, the receiver is physically implemented and tested. © 2011 Elsevier B.V. All rights reserved.This work was supported by the Spanish Ministerio de Educacion y Ciencia under grant TEC2008-06787.Canet Subiela, MJ.; Valls Coquillat, J.; Almenar Terré, V.; Marín-Roig Ramón, J. (2012). FPGA implementation of an OFDM-based WLAN receiver. Microprocessors and Microsystems. 36(3):232-244. https://doi.org/10.1016/j.micpro.2011.11.004S23224436

Investigating the relation between optimum guard interval and channel delay spread for a MC-CDMA system

This paper demonstrates a novel approach to determining the optimum guard interval for a multicarrier code division multiple access (MC-CDMA) system. Analytical expressions for useful and interference power are derived as a basis for comparison. From these, an expression for the signal-to-noise ratio of a detected bit is derived and used to determine the optimum guard interval for a given channel profile and system parameters. In contrast to other works, we use channel models based on actual measurements and we highlight important differences from theoretical models to support our approach. From our results, we propose an empirical rule for optimum guard intervals given prevailing channel parameters. We show that the optimum guard interval can be selected as the delay window that includes 95% and 99% multipath power for Es /N0 = 10 dB and Es /N0 = 20 dB, respectively. In our case, the optimum guard interval was between 2 τrms and 4 τrms for Es /N0 = 10 dB and between 3 τrms and 6.4 τrms for Es/N0 = 20 dB