Automated Verification of Design Patterns with LePUS3

Specification and [visual] modelling languages are expected to combine strong abstraction mechanisms with rigour, scalability, and parsimony. LePUS3 is a visual, object-oriented design description language axiomatized in a decidable subset of the first-order predicate logic. We demonstrate how LePUS3 is used to formally specify a structural design pattern and prove (‗verify‘) whether any JavaTM 1.4 program satisfies that specification. We also show how LePUS3 specifications (charts) are composed and how they are verified fully automatically in the Two-Tier Programming Toolkit

On the Verification of a WiMax Design Using Symbolic Simulation

In top-down multi-level design methodologies, design descriptions at higher levels of abstraction are incrementally refined to the final realizations. Simulation based techniques have traditionally been used to verify that such model refinements do not change the design functionality. Unfortunately, with computer simulations it is not possible to completely check that a design transformation is correct in a reasonable amount of time, as the number of test patterns required to do so increase exponentially with the number of system state variables. In this paper, we propose a methodology for the verification of conformance of models generated at higher levels of abstraction in the design process to the design specifications. We model the system behavior using sequence of recurrence equations. We then use symbolic simulation together with equivalence checking and property checking techniques for design verification. Using our proposed method, we have verified the equivalence of three WiMax system models at different levels of design abstraction, and the correctness of various system properties on those models. Our symbolic modeling and verification experiments show that the proposed verification methodology provides performance advantage over its numerical counterpart.Comment: In Proceedings SCSS 2012, arXiv:1307.802

Recognition and Verification of Design Patterns

In this paper we consider the automatic discovery of design (programming) patterns. While patterns have surfaced as an effective mechanism for authoring and understanding compelx software, popular languages lack facilities for direct specification of patterns or verification of pattern usage in program specifications. Static analysis for patterns is provably undecidable; we focus on discovery and verification of patterns by analyzing dynamic sequences of method calls on object. We show a proof-of-concept of our approach by presenting the results of analyzing a Java program for Iterator patterns

From RT-LOTOS to Time Petri Nets new foundations for a verification platform

The formal description technique RT-LOTOS has been selected as intermediate language to add formality to a real-time UML profile named TURTLE. For this sake, an RT-LOTOS verification platform has been developed for early detection of design errors in real-time system models. The paper discusses an extension of the platform by inclusion of verification tools developed for Time Petri Nets. The starting point is the definition of RT-LOTOS to TPN translation patterns. In particular, we introduce the concept of components embedding Time Petri Nets. The translation patterns are implemented in a prototype tool which takes as input an RT-LOTOS specification and outputs a TPN in the format admitted by the TINA tool. The efficiency of the proposed solution has been demonstrated on various case studies

Formal and efficient verification techniques for Real-Time UML models

The real-time UML profile TURTLE has a formal semantics expressed by translation into a timed process algebra: RT-LOTOS. RTL, the formal verification tool developed for RT-LOTOS, was first used to check TURTLE models against design errors. This paper opens new avenues for TURTLE model verification. It shows how recent work on translating RT-LOTOS specifications into Time Petri net model may be applied to TURTLE. RT-LOTOS to TPN translation patterns are presented. Their formal proof is the subject of another paper. These patterns have been implemented in a RT-LOTOS to TPN translator which has been interfaced with TINA, a Time Petri Net Analyzer which implements several reachability analysis procedures depending on the class of property to be verified. The paper illustrates the benefits of the TURTLE->RT-LOTOS->TPN transformation chain on an avionic case study

An Overview of Multi-layer Security System Using Biometrics

After years of research on biometrics, still the authentication and verification of a human being is at risk. Many challenges have been faced by the system to authenticate a human on the basis of their biometric trait. The design of this paper is such that it focuses on three main biometric techniques to extract the various features of a human body contour for authentication and verification purposes. This paper presents an approach towards voice recognition patterns, face geometry patterns and gait pattern analysis to increase the accuracy and precision of the system

A False Acceptance Error Controlling Method for Hyperspherical Classifiers

Controlling false acceptance errors is of critical importance in many pattern recognition applications, including signature and speaker verification problems. Toward this goal, this paper presents two post-processing methods to improve the performance of hyperspherical classifiers in rejecting patterns from unknown classes. The first method uses a self-organizational approach to design minimum radius hyperspheres, reducing the redundancy of the class region defined by the hyperspherical classifiers. The second method removes additional redundant class regions from the hyperspheres by using a clustering technique to generate a number of smaller hyperspheres. Simulation and experimental results demonstrate that by removing redundant regions these two post-processing methods can reduce the false acceptance error without significantly increasing the false rejection error