Microelectromechanical Systems for Wireless Radio Front-ends and Integrated Frequency References.

Microelectromechanical systems (MEMS) have great potential in realizing chip-scale integrated devices for energy-efficient analog spectrum processing. This thesis presents the development of a new class of MEMS resonators and filters integrated with CMOS readout circuits for RF front-ends and integrated timing applications. Circuit-level innovations coupled with new device designs allowed for realizing integrated systems with improved performance compared to standalone devices reported in the literature. The thesis is comprised of two major parts. The first part of the thesis is focused on developing integrated MEMS timing devices. Fused silica is explored as a new structural material for fabricating high-Q vibrating micromechanical resonators. A piezoelectric-on-silica MEMS resonator is demonstrated with a high Q of more than 20,000 and good electromechanical coupling. A low phase noise CMOS reference oscillator is implemented using the MEMS resonator as a mechanical frequency reference. Temperature-stable operation of the MEMS oscillator is realized by ovenizing the platform using an integrated heater. In an alternative scheme, the intrinsic temperature sensitivity of MEMS resonators is utilized for temperature sensing, and active compensation for MEMS oscillators is realized by oven-control using a phase-locked loop (PLL). CMOS circuits are implemented for realizing the PLL-based low-power oven-control system. The active compensation technique realizes a MEMS oscillator with an overall frequency drift within +/- 4 ppm across -40 to 70 °C, without the need for calibration. The CMOS PLL circuits for oven-control is demonstrated with near-zero phase noise invasion on the MEMS oscillators. The properties of PLL-based compensation for realizing ultra-stable MEMS frequency references are studied. In the second part of the thesis, RF MEMS devices, including tunable capacitors, high-Q inductors, and ohmic switches, are fabricated using a surface micromachined integrated passive device (IPD) process. Using this process, an integrated ultra-wideband (UWB) filter has been demonstrated, showing low loss and a small form factor. To further address the issue of narrow in-band interferences in UWB communication, a tunable MEMS bandstop filter is integrated with the bandpass filter with more than an octave frequency tuning range. The bandstop filter can be optionally switched off by employing MEMS ohmic switches co-integrated on the same chip.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/109069/1/zzwu_1.pd

Design, Fabrication, and Validation of a Highly Miniaturized Wirelessly Powered Neural Implant

We have recently witnessed an explosion in the number of neurons that can be recorded and/or stimulated simultaneously during neurophysiological experiments. Experiments have progressed from recording or stimulation with a single electrode to Micro-Electrode Array (MEA) such as the Utah Array. These MEAs can be instrumented with current drivers, neural amplifiers, digitizers and wireless communication links. The broad interest in these MEAs suggests that there is a need for large scale neural recording and stimulation. The ultimate goal is to coordinate the recordings and stimulation of potentially thousands of neurons from many brain areas. Unfortunately, current state-of-the-art MEAs are limited by their scalability and long-term stability because of their physical size and rigid configuration. Furthermore, some applications prioritize a distributed neural interface over one that offers high resolution. Examples of biomedical applications that necessitate an interface with neurons from many sites in the brain include: i) understanding and treating neurological disorders that affect distributed locations throughout the CNS; ii) revolutionizing our understanding of the brain by studying the correlations between neural networks from different regions of the brain and the mechanisms of cognitive functions; and iii) covering larger area in the sensorimotor cortex of amputees to more accurately control robotic prosthetic limbs or better evoke a sense of touch. One solution to make large scale, fully specifiable, electrical stimulation and recording possible, is to disconnect the electrodes from the base, so that they can be arbitrarily placed, using a syringe, freely in the nervous system. To overcome the challenges of system miniaturization, we propose the “microbead”, an ultra-small neural stimulating implant, that is currently implemented in a 130nm CMOS technology with the following characteristics: 200 μm × 200 μm × 80 μm size; optimized wireless powering, all micro-electronics on single chip; and integrated electrodes and coil. The stimulating microbead is validated in a sciatic nerve by generating leg movements. A recording microbead is also investigated with following characteristics: wireless powering using steerable phased coil array, miniaturized front-end, and backscattering telemetry. These microbeads could eventually replace the rigid arrays that are currently the state-of-the-art in electrophysiology set-ups

Ultra wide-bandwidth micro energy harvester

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 189-197).An ultra wide-bandwidth resonating thin film PZT MEMS energy harvester has been designed, modeled, fabricated and tested. It harvests energy from parasitic ambient vibration at a wide range of amplitude and frequency via piezoelectric effect. At the present time, the designs of most piezoelectric energy devices have been based on high-Q linear cantilever beams that use the bending strain to generate electrical charge via piezoelectric effect. They suffer from very small bandwidth and low power density which prevents them from practical use. Contrarily, the new design utilizes the tensile stretching strain in doubly-anchored beams. The resultant stiffness nonlinearity due to the stretching provides a passive feedback and consequently a wide-band resonance. This wide bandwidth of resonance enables a robust power generation amid the uncertainty of the input vibration spectrum. The device is micro-fabricated by a combination of surface and bulk micro-machining processes. Released devices are packaged, poled and electro-mechanically tested to verify the wide-bandwidth nonlinear behavior of the system. Two orders of magnitude improvement in bandwidth and power density is demonstrated by comparing the frequency response of the system with that of an equivalent linear harvester with a similar Q-factor.by Arman Hajati.Ph.D

Synthesis and monolithic integration of analogue signal processing networks

Data traffic of future 5G telecommunication systems is projected to increase 10 000-fold compared to current rates. 5G fronthaul links are therefore expected to operate in the mm-wave spectrum with some preliminary International Telecommunication Union specifications set for the 71-76 and 81-86 GHz bands. Processing 5 GHz as a single contiguous band in real-time, using existing digital signal processing (DSP) systems, is exceedingly challenging. A similar challenge exists in radio astronomy, with the Square Kilometer Array project expecting data throughput rates of 15 Tbits/s at its completion. Speed improvements on existing state-of-the-art DSPs of 2-3 orders of magnitude are therefore required to meet future demands. One possible mitigating approach to processing wideband data in real-time is to replace some DSP blocks with analog signal processing (ASP) equivalents, since analogue devices outperform their digital counterparts in terms of cost, power consumption and the maximum attainable bandwidth. The fundamental building block of any ASP is an all-pass network of prescribed response, which can always be synthesized by cascaded first- and second-order all-pass sections (with two cascaded first-order sections being a special case of the latter). The monolithic integration of all-pass networks in commercial CMOS and BiCMOS technology nodes is a key consideration for commercial adaptation of ASPs, since it supports mass production at reduced costs and operating power requirements, making the ASP approach feasible. However, this integration has presented a number of yet unsolved challenges. Firstly, the state-of-the-art methods for synthesizing quasi-arbitrary group delay functions using all-pass elements lack a theoretical synthesis procedure that guarantees minimum-order networks. In this work an analytically-based solution to the synthesis problem is presented that produces an all-pass network with a response approximating the required group delay to within an arbitrary minimax error. This method is shown to work for any physical realization of second-order all-pass elements, is guaranteed to converge to a global optimum solution without any choice of seed values as an input, and allows synthesis of pre-defined networks described either analytically or numerically. Secondly, second-order all-pass networks are currently primarily implemented in off-chip planar media, which is unsuited for high volume production. Component sensitivity, process tolerances and on-chip parasitics often make proposed on-chip designs impractical. Consequently, to date, no measured results of a dispersive on-chip second-order all-pass network suitable for ASP applications (delay Q-value (QD) larger than 1) have been presented in either CMOS or BiCMOS technology nodes. In this work, the first ever on-chip CMOS second-order all-pass network is proposed with a measured QD-value larger than 1. Measurements indicate a post-tuning bandwidth of 280 MHz, peak-to-nominal delay variation of 10 ns, QD-value of 1.15 and magnitude variation of 3.1 dB. An active on-chip mm-wave second-order all-pass network is further demonstrated in a 130 nm SiGe BiCMOS technology node with a bandwidth of 40 GHz, peak-to-nominal delay of 62 ps, QD-value of 3.6 and a magnitude ripple of 1.4 dB. This is the first time that measurement results of a mm-wave bandwidth second-order all-pass network have been reported. This work therefore presents the first step to monolithically integrating ASP solutions to conventional DSP problems, thereby enabling ultra-wideband signal processing on-chip in commercial technology nodes.Thesis (PhD)--University of Pretoria, 2018.Square Kilometer Array (SKA) project - postgraduate scholarshipElectrical, Electronic and Computer EngineeringPhDUnrestricte

INTEGRATION OF CMOS TECHNOLOGY INTO LAB-ON-CHIP SYSTEMS APPLIED TO THE DEVELOPMENT OF A BIOELECTRONIC NOSE

This work addresses the development of a lab-on-a-chip (LOC) system for olfactory sensing. The method of sensing employed is cell-based, utilizing living cells to sense stimuli that are otherwise not easily sensed using conventional transduction techniques. Cells have evolved over millions of years to be exquisitely sensitive to their environment, with certain types of cells producing electrical signals in response to stimuli. The core device that is introduced here is comprised of living olfactory sensory neurons (OSNs) on top of a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC). This hybrid bioelectronic approach to sensing leverages the sensitivity of OSNs with the electronic signal processing capability of modern ICs. Intimately combining electronics with biology presents a number of unique challenges to integration that arise from the disparate requirements of the two separate domains. Fundamentally the obstacles arise from the facts that electronic devices are designed to work in dry environments while biology requires not only a wet environment, but also one that is precisely controlled and non-toxic. Design and modeling of such heterogeneously integrated systems is complicated by the lack of tools that can address the multiple domains and techniques required for integration, namely IC design, fluidics, packaging, and microfabrication, and cell culture. There also arises the issue of how to handle the vast amount of data that can be generated by such systems, and specifically how to efficiently identify signals of interest and communicate them off-chip. The primary contributions of this work are the development of a new packaging scheme for integration of CMOS ICs into fluidic LOC systems, a methodology for cross-coupled multi-domain iterative modeling of heterogeneously integrated systems, demonstration of a proof-of-concept bioelectronic olfactory sensor, and a novel event-based technique to minimize the bandwidth required to communicate the information contained in bio-potential signals produced by dense arrays of electrically active cells

Time resolved single photon imaging in Nanometer Scale CMOS technology

Time resolved imaging is concerned with the measurement of photon arrival time. It has a wealth of emerging applications including biomedical uses such as fluorescence lifetime microscopy and positron emission tomography, as well as laser ranging and imaging in three dimensions. The impact of time resolved imaging on human life is significant: it can be used to identify cancerous cells in-vivo, how well new drugs may perform, or to guide a robot around a factory or hospital. Two essential building blocks of a time resolved imaging system are a photon detector capable of sensing single photons, and fast time resolvers that can measure the time of flight of light to picosecond resolution. In order to address these emerging applications, miniaturised, single-chip, integrated arrays of photon detectors and time resolvers must be developed with state of the art performance and low cost. The goal of this research is therefore the design, layout and verification of arrays of low noise Single Photon Avalanche Diodes (SPADs) together with high resolution Time-Digital Converters (TDCs) using an advanced silicon fabrication process. The research reported in this Thesis was carried out as part of the E.U. funded Megaframe FP6 Project. A 32x32 pixel, one million frames per second, time correlated imaging device has been designed, simulated and fabricated using a 130nm CMOS Imaging process from ST Microelectronics. The imager array has been implemented together with required support cells in order to transmit data off chip at high speed as well as providing a means of device control, test and calibration. The fabricated imaging device successfully demonstrates the research objectives. The Thesis presents details of design, simulation and characterisation results of the elements of the Megaframe device which were the author’s own work. Highlights of the results include the smallest and lowest noise SPAD devices yet published for this class of fabrication process and an imaging array capable of recording single photon arrivals every microsecond, with a minimum time resolution of fifty picoseconds and single bit linearity

INTER-ENG 2020

These proceedings contain research papers that were accepted for presentation at the 14th International Conference Inter-Eng 2020 ,Interdisciplinarity in Engineering, which was held on 8–9 October 2020, in Târgu Mureș, Romania. It is a leading international professional and scientific forum for engineers and scientists to present research works, contributions, and recent developments, as well as current practices in engineering, which is falling into a tradition of important scientific events occurring at Faculty of Engineering and Information Technology in the George Emil Palade University of Medicine, Pharmacy Science, and Technology of Târgu Mures, Romania. The Inter-Eng conference started from the observation that in the 21st century, the era of high technology, without new approaches in research, we cannot speak of a harmonious society. The theme of the conference, proposing a new approach related to Industry 4.0, was the development of a new generation of smart factories based on the manufacturing and assembly process digitalization, related to advanced manufacturing technology, lean manufacturing, sustainable manufacturing, additive manufacturing, and manufacturing tools and equipment. The conference slogan was “Europe’s future is digital: a broad vision of the Industry 4.0 concept beyond direct manufacturing in the company”