19,825 research outputs found
A Graph Rewriting Approach for Transformational Design of Digital Systems
Transformational design integrates design and verification. It combines âcorrectness by constructionâ and design creativity by the use of pre-proven behaviour preserving transformations as design steps. The formal aspects of this methodology are hidden in the transformations. A constraint is the availability of a design representation with a compositional formal semantics. Graph representations are useful design representations because of their visualisation of design information. In this paper graph rewriting theory, as developed in the last twenty years in mathematics, is shown to be a useful basis for a formal framework for transformational design. The semantic aspects of graphs which are no part of graph rewriting theory are included by the use of attributed graphs. The used attribute algebra, table algebra, is a relation algebra derived from database theory. The combination of graph rewriting, table algebra and transformational design is new
A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors
Smart systems are characterized by the integration in a single device of multi-domain subsystems of different technological domains, namely, analog, digital, discrete and power devices, MEMS, and power sources. Such challenges, emerging from the heterogeneous nature of the whole system, combined with the traditional challenges of digital design, directly impact on performance and on propagation delay of digital components. This article proposes a design approach to enhance the RTL model of a given digital component for the integration in smart systems with the automatic insertion of delay sensors, which can detect and correct timing failures. The article then proposes a methodology to verify such added features at system level. The augmented model is abstracted to SystemC TLM, which is automatically injected with mutants (i.e., code mutations) to emulate delays and timing failures. The resulting TLM model is finally simulated to identify timing failures and to verify the correctness of the inserted delay monitors. Experimental results demonstrate the applicability of the proposed design and verification methodology, thanks to an efficient sensor-aware abstraction methodology, by applying the flow to three complex case studies
Five-Axis Machine Tool Condition Monitoring Using dSPACE Real-Time System
This paper presents the design, development and SIMULINK implementation of the lumped parameter model of C-axis drive from GEISS five-axis CNC machine tool. The simulated results compare well with the experimental data measured from the actual machine. Also the paper describes the steps for data acquisition using ControlDesk and hardware-in-the-loop implementation of the drive models in dSPACE real-time system. The main components of the HIL system are: the drive model simulation and input â output (I/O) modules for receiving the real controller outputs. The paper explains how the experimental data obtained from the data acquisition process using dSPACE real-time system can be used for the development of machine tool diagnosis and prognosis systems that facilitate the improvement of maintenance activities
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Coriolis flowmeters: A review of developments over the past 20 years, and an assessment of the state of the art and likely future directions
This paper starts from a brief revisit of key early published work so that an overview of modern Coriolis flowmeters can be provided based on a historical background. The paper, then, focuses on providing an updated review of Coriolis flow measurement technology over the past 20 years. Published research work and industrial Coriolis flowmeter design are both reviewed in details. It is the intention of this paper to provide a comprehensive review study of all important topics in the subject, which include interesting theoretical and experimental studies and innovative industrial developments and applications. The advances in fundamental understanding and technology development are clearly identified. Future directions in various areas together with some open questions are also outlined.This is the accepted manuscript version. The final version is available from Elsevier at http://dx.doi.org/10.1016/j.flowmeasinst.2014.08.01
Elastic bundles :modelling and architecting asynchronous circuits with granular rigidity
PhD ThesisIntegrated Circuit (IC) designs these days are predominantly System-on-Chips (SoCs).
The complexity of designing a SoC has increased rapidly over the years due to growing
process and environmental variations coupled with global clock distribution di culty.
Moreover, traditional synchronous design is not apt to handle the heterogeneous timing
nature of modern SoCs. As a countermeasure, the semiconductor industry witnessed
a strong revival of asynchronous design principles. A new paradigm of digital circuits
emerged, as a result, namely mixed synchronous-asynchronous circuits. With a wave
of recent innovations in synchronous-asynchronous CAD integration, this paradigm is
showing signs of commercial adoption in future SoCs mainly due to the scope for reuse
of synchronous functional blocks and IP cores, and the co-existence of synchronous and
asynchronous design styles in a common EDA framework.
However, there is a lack of formal methods and tools to facilitate mixed synchronousasynchronous
design. In this thesis, we propose a formal model based on Petri nets with
step semantics to describe these circuits behaviourally. Implication of this model in the
veri cation and synthesis of mixed synchronous-asynchronous circuits is studied. Till
date, this paradigm has been mainly explored on the basis of Globally Asynchronous
Locally Synchronous (GALS) systems. Despite decades of research, GALS design has
failed to gain traction commercially. To understand its drawbacks, a simulation framework
characterising the physical and functional aspects of GALS SoCs is presented.
A novel method for synthesising mixed synchronous-asynchronous circuits with varying
levels of rigidity is proposed. Starting with a high-level data ow model of a system which
is intrinsically asynchronous, the key idea is to introduce rigidity of chosen granularity
levels in the model without changing functional behaviour. The system is then partitioned
into functional blocks of synchronous and asynchronous elements before being transformed
into an equivalent circuit which can be synthesised using standard EDA tools
European White Book on Real-Time Power Hardware in the Loop Testing : DERlab Report No. R- 005.0
The European White Book on Real-Time-Powerhardware-in-the-Loop testing is intended to serve as a reference document on the future of testing of electrical power equipment, with speciïŹ c focus on the emerging hardware-in-the-loop activities and application thereof within testing facilities and procedures. It will provide an outlook of how this powerful tool can be utilised to support the development, testing and validation of speciïŹ cally DER equipment. It aims to report on international experience gained thus far and provides case studies on developments and speciïŹ c technical issues, such as the hardware/software interface. This white book compliments the already existing series of DERlab European white books, covering topics such as grid-inverters and grid-connected storag
FPGA Architecture Optimization Using Geometric Programming
Volume 4 No 13 of the periodical Progression. Published November, February, May and August by The Radiant Healing Centre. SPCL PER BT 732 P76 V.1,1932-V.5,193
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