64 research outputs found

    SIMD acceleration for HEVC decoding

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    Single instruction multiple data (SIMD) instructions have been commonly used to accelerate video codecs. The recently introduced High Efficiency Video Coding (HEVC) codec like its predecessors is based on the hybrid video codec principle and, therefore, is also well suited to be accelerated with SIMD. In this paper we present the SIMD optimization for the entire HEVC decoder for all major SIMD instruction set architectures. Evaluation has been performed on 14 mobile and PC platforms covering most major architectures released in recent years. With SIMD, up to 5× speedup can be achieved over the entire HEVC decoder, resulting in up to 133 and 37.8 frames/s on average on a single core for Main profile 1080p and Main10 profile 2160p sequences, respectively.EC/FP7/288653/EU/Low-Power Parallel Computing on GPUs/LPGP

    Mixed-Resolution HEVC based multiview video codec for low bitrate transmission

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    SIMD Acceleration for HEVC Decoding

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    High-Level Synthesis Based VLSI Architectures for Video Coding

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    High Efficiency Video Coding (HEVC) is state-of-the-art video coding standard. Emerging applications like free-viewpoint video, 360degree video, augmented reality, 3D movies etc. require standardized extensions of HEVC. The standardized extensions of HEVC include HEVC Scalable Video Coding (SHVC), HEVC Multiview Video Coding (MV-HEVC), MV-HEVC+ Depth (3D-HEVC) and HEVC Screen Content Coding. 3D-HEVC is used for applications like view synthesis generation, free-viewpoint video. Coding and transmission of depth maps in 3D-HEVC is used for the virtual view synthesis by the algorithms like Depth Image Based Rendering (DIBR). As first step, we performed the profiling of the 3D-HEVC standard. Computational intensive parts of the standard are identified for the efficient hardware implementation. One of the computational intensive part of the 3D-HEVC, HEVC and H.264/AVC is the Interpolation Filtering used for Fractional Motion Estimation (FME). The hardware implementation of the interpolation filtering is carried out using High-Level Synthesis (HLS) tools. Xilinx Vivado Design Suite is used for the HLS implementation of the interpolation filters of HEVC and H.264/AVC. The complexity of the digital systems is greatly increased. High-Level Synthesis is the methodology which offers great benefits such as late architectural or functional changes without time consuming in rewriting of RTL-code, algorithms can be tested and evaluated early in the design cycle and development of accurate models against which the final hardware can be verified

    HEVC Based Frame Interleaved Coding Technique for Stereo and Multi-View Videos

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    The standard HEVC codec and its extension for coding multiview videos, known as MV-HEVC, have proven to deliver improved visual quality compared to its predecessor, H.264/MPEG-4 AVC’s multiview extension, H.264-MVC, for the same frame resolution with up to 50% bitrate savings. MV-HEVC’s framework is similar to that of H.264-MVC, which uses a multi-layer coding approach. Hence, MV-HEVC would require all frames from other reference layers decoded prior to decoding a new layer. Thus, the multi-layer coding architecture would be a bottleneck when it comes to quicker frame streaming across different views. In this paper, an HEVC-based Frame Interleaved Stereo/Multiview Video Codec (HEVC-FISMVC) that uses a single layer encoding approach to encode stereo and multiview video sequences is presented. The frames of stereo or multiview video sequences are interleaved in such a way that encoding the resulting monoscopic video stream would maximize the exploitation of temporal, inter-view, and cross-view correlations and thus improving the overall coding efficiency. The coding performance of the proposed HEVC-FISMVC codec is assessed and compared with that of the standard MV-HEVC’s performance for three standard multi-view video sequences, namely: “Poznan_Street”, “Kendo” and “Newspaper1”. Experimental results show that the proposed codec provides more substantial coding gains than the anchor MV-HEVC for coding both stereo and multi-view video sequences

    Pengurangan Kompleksitas Komputasi Pada Multiview HEVC Berbasis Perangkat FPGA

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    Dengan meningkatnya kualitas dan resolusi konten video, terutama video 3D, kompleksitas komputasi dalam pemrosesannya juga meningkat secara signifikan. Salah satu standar video yang populer, HEVC memiliki ekstensi yang dinamakan Multiview HEVC (MV-HEVC) dan 3D-HEVC dengan jumlah data dan resolusi yang tinggi, mengakibatkan adanya peningkatan kompleksitas komputasi. Penelitian ini bertujuan mengurangi kompleksitas komputasi dari video MV-HEVC dengan menerapkan mode decision berupa ECU, CFM, ESD, dan deblocking filter yang diujicobakan pada platform PC berbasis Linux dan platform Xilinx All Programmable SoC. Dari hasil eksperimen didapatkan pengurangan kompleksitas komputasi yang dilihat dari perbandingan dari waktu encoding. Platform Xilinx All Programmable SoC mampu memperoleh waktu encoding yang lebih cepat 35,85% daripada PC berbasis Linux. Selanjutnya untuk kualitas video yang dihasilkan antara kedua platform tersebut hampir sama dilihat dari nilai bitrate dan PSNR. =========================================================================== Due to the increasing quality and resolution of videocontent, especially 3D video, the computational complexity forits processing also significantly increases. One of the popularformat, HEVC has extensions called Multiview HEVC (MV-HEVC) and 3D-HEVC with high amounts of data and highresolution that resulting in increased computational complexity.This study aims to reduce the computational complexity of MVHEVC videos by implementing mode decision such as ECU,CFM, ESD, and deblocking filterswhich are tested on Linuxbased PC platforms and the Xilinx All Programmable SoCplatform. From the experimental results obtained the reductionin computational complexity can be seen from the comparisonofencoding time, the Xilinx All Programmable SoC platform isable to obtain encoding times that are faster than Linux-basedPCs. For the quality of the video produced between the two theplatform is not significant from the bitrate and PSNR values

    Learning Clustering-Based Linear Mappings for Quantization Noise Removal

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    International audienceThis paper describes a novel scheme to reduce the quantization noise of compressed videos and improve the overall coding performances. The proposed scheme first consists in clustering noisy patches of the compressed sequence. Then, at the encoder side, linear mappings are learned for each cluster between the noisy patches and the corresponding source patches. The linear mappings are then transmitted to the decoder where they can be applied to perform de-noising. The method has been tested with the HEVC standard, leading to a bitrate saving of up to 9.63%

    Efficient HEVC-based video adaptation using transcoding

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    In a video transmission system, it is important to take into account the great diversity of the network/end-user constraints. On the one hand, video content is typically streamed over a network that is characterized by different bandwidth capacities. In many cases, the bandwidth is insufficient to transfer the video at its original quality. On the other hand, a single video is often played by multiple devices like PCs, laptops, and cell phones. Obviously, a single video would not satisfy their different constraints. These diversities of the network and devices capacity lead to the need for video adaptation techniques, e.g., a reduction of the bit rate or spatial resolution. Video transcoding, which modifies a property of the video without the change of the coding format, has been well-known as an efficient adaptation solution. However, this approach comes along with a high computational complexity, resulting in huge energy consumption in the network and possibly network latency. This presentation provides several optimization strategies for the transcoding process of HEVC (the latest High Efficiency Video Coding standard) video streams. First, the computational complexity of a bit rate transcoder (transrater) is reduced. We proposed several techniques to speed-up the encoder of a transrater, notably a machine-learning-based approach and a novel coding-mode evaluation strategy have been proposed. Moreover, the motion estimation process of the encoder has been optimized with the use of decision theory and the proposed fast search patterns. Second, the issues and challenges of a spatial transcoder have been solved by using machine-learning algorithms. Thanks to their great performance, the proposed techniques are expected to significantly help HEVC gain popularity in a wide range of modern multimedia applications

    HEVC based Mixed-Resolution Stereo Video Codec

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    This paper presents a High Efficiency Video Codec (HEVC) based spatial mixed-resolution stereo video codec. The proposed codec applies a frame interleaving algorithm to reorder the stereo video frames into a monoscopic video. The challenge for mixed-resolution video coding is to enable the codec to encode frames with different frame resolutions. This issue is addressed by superimposing a low resolution replica of the decoded I-frame on its respective decoded picture, where remaining space of the frame is set to zero. This significantly reduces the computation cost for finding the best match. The proposed codec’s reference frames structure is designed to efficiently exploit both temporal and inter-view correlations. Performance of the proposed codec is assessed using five standard multiview video datasets and benchmarked against that of the anchor and the state-of-the-art techniques. Results show that the proposed codec yields significantly higher coding performance compared to the anchor and state-of-the-art techniques
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