Data-structure builder for VLSI/CAD software

Relational database systems have successfully solved many business data processing problems. The primary reason of this success is that the relational data model provides a simple, yet flexible view of data as tables. In studying VLSI/CAD data, we noticed that they are often represented in formats similar to relational tuples. Therefore, they can be stored easily in relational tables. However, it is generally agreed that conventional relational database systems are inefficient for VLSI/CAD applications, since such applications often access large amounts of data repetitively. In order to solve this problem, we designed and implemented a data mapping subsystem that converts VLSI/CAD data stored in relational tables into internal data structures so that they can be efficiently manipulated in C. By using our data mapping language, we could reduce the amount of code required by the data-structure construction parts of some real VLSI/ CAD tools to about 1/10 of that required by C implementation. Our data-structure builder consumes several times more CPU cycles

STRICT: a language and tool set for the design of very large scale integrated circuits

PhD ThesisAn essential requirement for the design of large VLSI circuits is a design methodology which would allow the designer to overcome the complexity and correctness issues associated with the building of such circuits. We propose that many of the problems of the design of large circuits can be solved by using a formal design notation based upon the functional programming paradigm, that embodies design concepts that have been used extensively as the framework for software construction. The design notation should permit parallel, sequential, and recursive decompositions of a design into smaller components, and it should allow large circuits to be constructed from simpler circuits that can be embedded in a design in a modular fashion. Consistency checking should be provided as early as possible in a design. Such a methodology would structure the design of a circuit in much the same way that procedures, classes, and control structures may be used to structure large software systems. However, such a design notation must be supported by tools which automatically check the consistency of the design, if the methodology is to be practical. In principle, the methodology should impose constraints upon circuit design to reduce errors and provide' correctness by construction' . It should be possible to generate efficient and correct circuits, by providing a route to a large variety of design tools commonly found in design systems: simulators, automatic placement and routing tools, module generators, schematic capture tools, and formal verification and synthesis tools

Конвертация топологических данных с использованием параллельных вычислений

В статье рассмотрены алгоритмы конвертации топологических данных из форматов САПР в формат Т29 (формат установок автоматического контроля топологических структур на фотошаблонах производства УП «КБТЭМ-ОМО»), который напрямую не поддерживается современными САПР. Особенность таких данных – большой объем данных и, следовательно, время конвертации. Использование параллельных методов вычислений на базе ПЭВМ с многоядерным процессором и технологии OpenMP позволяет значительно ускорить время обработки данных.У статті розглянуті алгоритми конвертації топологічних даних з форматів САПР у формат Т29 (формат установок автоматичного контролю топологічних структур на фотошаблонах виробництва УП «КБТЕМ-ОМО»), який прямо не підтримується сучасними САПР. Особливість таких даних – великий обсяг даних і, відповідно, час конвертації. Використання паралельних методів обчислень на базі ПЕОМ з багатоядерним процесором і технології OpenMP дозволяє значно прискорити час обробки даних.In this paper, we propose algorithms and software for parallel implementation of conversion of VLSI Layout Data from CAD format Gerber and MEBES into an internal representation and then into format of automatic mask inspection system T29. The software is developed on basis of OpenMP technology to work on PC with 4-core processor. It is shown that using parallel computing speeds up a conversion process. In the future we are planning to develop similar tools for data conversion from CIF and DFX formats into the internal format, and further into format GDS-II. These tools allow developing a program complex of topological data processing to work with automatic mask inspection system made by R&D Company “KBTEM-OMO” of “Planar” Corporation

FPGA implementation of a frame delay

The objective of this thesis is to investigate the applicability of Field Programmable Gate Arrays (FPGAs) for frame delay implementation. FPGAs are programmable devices that can be directly configured by the end user without the use of an integrated circuit fabrication facility. They offer the designer the benefits of custom hardware, eliminating high development costs and manufacturing time. Frame delays are easier to realize using R/W memory where data is written into the memory and read out for each frame. FPGAs are used in a Quartus II environment as it is easy to perform frame delay implementation using schematic entry procedure. Since FPGAs use look-up tables as configurable logic blocks, they are considered as an appropriate choice for frame delay based designs

Network Interface Design for Network-on-Chip

In the culture of globalized integrated circuit (IC, a.k.a chip) production, the use of Intellectual Property (IP) cores, computer aided design tools (CAD) and testing services from un-trusted vendors are prevalent to reduce the time to market. Unfortunately, the globalized business model potentially creates opportunities for hardware tampering and modification from adversary, and this tampering is known as hardware Trojan (HT). Network-on-chip (NoC) has emerged as an efficient on-chip communication infrastructure. In this work, the security aspects of NoC network interface (NI), one of the most critical components in NoC will be investigated and presented. Particularly, the NI design, hardware attack models and countermeasures for NI in a NoC system are explored. An OCP compatible NI is implemented in an IBM0.18ìm CMOS technology. The synthesis results are presented and compared with existing literature. Second, comprehensive hardware attack models targeted for NI are presented from system level to circuit level. The impact of hardware Trojans on NoC functionality and performance are evaluated. Finally, a countermeasure method is proposed to address the hardware attacks in NIs