Real-time audio spectrum analyser research, design, development and implementation using the 32 bit ARMR Cortex-M4 microcontroller

This thesis describes the design and testing of a low-cost hand-held real-time audio analyser (RTAA). This includes the design of an embedded system, the development of the firmware executed by the embedded system, and the implementation of a real-time signal processing algorithms. One of the objectives of this project was to design an alternative low-cost audio analyser to the current commercially available solutions. The device was tested with the audio standard test signal (pink noise) and was compared to the expected at-spectrum response corresponding to a balanced audio system. The design makes use of an 32-bit Reduced Instruction Set Computer (RISC) processor core (ARM Cortex-M4), namely the STM32F4 family of microcontrollers. Due to the pin compatibility of the microcontroller (designed and manufactured by STMicroelectronics), the new development board can also be upgraded with the newly released Cortex-M7 microcontroller, namely the STM32F7 family of microcontrollers. Moreover, the low-cost hardware design features 256kB Random Access Memory (RAM); on-board Micro-Electro-Mechanical System (MEMS) microphone; on-chip 12-bit Analogue-to-Digital (A/D) and Digital-to-Analogue (D/A) Converters; 3.2" Thin-Film-Transistor Liquid-Crystal Display (TFT-LCD) with a resistive touch screen sensor and SD-Card Socket. Furthermore, two additional expansion modules were designed and can extend the functionality of the designed real-time audio analyser. Firstly, an audio/video module featuring a professional 24-bit 192kHz sampling rate audio CODEC; balanced audio microphone input; unbalanced line output; three MEMS microphone inputs; headphone output; and a Video Graphics Array (VGA) controller allowing the display of the analysed audio spectrum on either a projector or monitor. The second expansion module features two external memories: 1MB Static Random Access Memory (SRAM) and 16MB Synchronous Dynamic Random Access Memory (SDRAM). While the two additional expansion modules were not completely utilised by the firmware presented in this thesis, upgrades of the real-time audio analyser firmware in future revisions will provide a higher performing and more accurate analysis of the audio spectrum. The full research and design process for the real-time audio analyser is discussed and both Problems and pitfalls with the final implemented design are highlighted and possible resolutions were investigated. The development costs (excluding labour) are given in the form of a bill of materials (BOM) with the total costs averaging around R1000. Moreover, the additional VGA controller could further decrease the overall costs with the removal of the TFT-LCD screen from the audio analyser and provided the external display was not included in the BOM

Characterization of Impulse Noise and Hazard Analysis of Impulse Noise Induced Hearing Loss using AHAAH Modeling

Millions of people across the world are suffering from noise induced hearing loss (NIHL), especially under working conditions of either continuous Gaussian or non-Gaussian noise that might affect human\u27s hearing function. Impulse noise is a typical non-Gaussian noise exposure in military and industry, and generates severe hearing loss problem. This study mainly focuses on characterization of impulse noise using digital signal analysis method and prediction of the auditory hazard of impulse noise induced hearing loss by the Auditory Hazard Assessment Algorithm for Humans (AHAAH) modeling. A digital noise exposure system has been developed to produce impulse noises with peak sound pressure level (SPL) up to 160 dB. The characterization of impulse noise generated by the system has been investigated and analyzed in both time and frequency domains. Furthermore, the effects of key parameters of impulse noise on auditory risk unit (ARU) are investigated using both simulated and experimental measured impulse noise signals in the AHAAH model. The results showed that the ARUs increased monotonically with the peak pressure (both P+ and P-) increasing. With increasing of the time duration, the ARUs increased first and then decreased, and the peak of ARUs appeared at about t = 0.2 ms (for both t+ and t-). In addition, the auditory hazard of experimental measured impulse noises signals demonstrated a monotonically increasing relationship between ARUs and system voltages

Ultra-low-power circuits and systems for wearable and implantable medical devices

Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (pages 219-231).Advances in circuits, sensors, and energy storage elements have opened up many new possibilities in the health industry. In the area of wearable devices, the miniaturization of electronics has spurred the rapid development of wearable vital signs, activity, and fitness monitors. Maximizing the time between battery recharge places stringent requirements on power consumption by the device. For implantable devices, the situation is exacerbated by the fact that energy storage capacity is limited by volume constraints, and frequent battery replacement via surgery is undesirable. In this case, the design of energy-efficient circuits and systems becomes even more crucial. This thesis explores the design of energy-efficient circuits and systems for two medical applications. The first half of the thesis focuses on the design and implementation of an ultra-low-power, mixed-signal front-end for a wearable ECG monitor in a 0.18pm CMOS process. A mixed-signal architecture together with analog circuit optimizations enable ultra-low-voltage operation at 0.6V which provides power savings through voltage scaling, and ensures compatibility with state-of-the-art DSPs. The fully-integrated front-end consumes just 2.9[mu]W, which is two orders of magnitude lower than commercially available parts. The second half of this thesis focuses on ultra-low-power system design and energy-efficient neural stimulation for a proof-of-concept fully-implantable cochlear implant. First, implantable acoustic sensing is demonstrated by sensing the motion of a human cadaveric middle ear with a piezoelectric sensor. Second, alternate energy-efficient electrical stimulation waveforms are investigated to reduce neural stimulation power when compared to the conventional rectangular waveform. The energy-optimal waveform is analyzed using a computational nerve fiber model, and validated with in-vivo ECAP recordings in the auditory nerve of two cats and with psychophysical tests in two human cochlear implant users. Preliminary human subject testing shows that charge and energy savings of 20-30% and 15-35% respectively are possible with alternative waveforms. A system-on-chip comprising the sensor interface, reconfigurable sound processor, and arbitrary-waveform neural stimulator is implemented in a 0.18[mu]m high-voltage CMOS process to demonstrate the feasibility of this system. The sensor interface and sound processor consume just 12[mu]W of power, representing just 2% of the overall system power which is dominated by stimulation. As a result, the energy savings from using alternative stimulation waveforms transfer directly to the system.by Marcus Yip.Ph.D

NASA Tech Briefs, April 1993

Topics include: Optoelectronics; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery; Fabrication Technology; Mathematics and Information Sciences; Life Sciences

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits