493 research outputs found
Exploiting heterogeneity in Chip-Multiprocessor Design
In the past decade, semiconductor manufacturers are persistent in building faster and smaller transistors in order to boost the processor performance as projected by Moore’s Law. Recently, as we enter the deep submicron regime, continuing the same processor development pace becomes an increasingly difficult issue due to constraints on power, temperature, and the scalability of transistors. To overcome these challenges, researchers propose several innovations at both architecture and device levels that are able to partially solve the problems. These diversities in processor architecture and manufacturing materials provide solutions to continuing Moore’s Law by effectively exploiting the heterogeneity, however, they also introduce a set of unprecedented challenges that have been rarely addressed in prior works. In this dissertation, we present a series of in-depth studies to comprehensively investigate the design and optimization of future multi-core and many-core platforms through exploiting heteroge-neities. First, we explore a large design space of heterogeneous chip multiprocessors by exploiting the architectural- and device-level heterogeneities, aiming to identify the optimal design patterns leading to attractive energy- and cost-efficiencies in the pre-silicon stage. After this high-level study, we pay specific attention to the architectural asymmetry, aiming at developing a heterogeneity-aware task scheduler to optimize the energy-efficiency on a given single-ISA heterogeneous multi-processor. An advanced statistical tool is employed to facilitate the algorithm development. In the third study, we shift our concentration to the device-level heterogeneity and propose to effectively leverage the advantages provided by different materials to solve the increasingly important reliability issue for future processors
Intelligent Management of Mobile Systems through Computational Self-Awareness
Runtime resource management for many-core systems is increasingly complex.
The complexity can be due to diverse workload characteristics with conflicting
demands, or limited shared resources such as memory bandwidth and power.
Resource management strategies for many-core systems must distribute shared
resource(s) appropriately across workloads, while coordinating the high-level
system goals at runtime in a scalable and robust manner.
To address the complexity of dynamic resource management in many-core
systems, state-of-the-art techniques that use heuristics have been proposed.
These methods lack the formalism in providing robustness against unexpected
runtime behavior. One of the common solutions for this problem is to deploy
classical control approaches with bounds and formal guarantees. Traditional
control theoretic methods lack the ability to adapt to (1) changing goals at
runtime (i.e., self-adaptivity), and (2) changing dynamics of the modeled
system (i.e., self-optimization).
In this chapter, we explore adaptive resource management techniques that
provide self-optimization and self-adaptivity by employing principles of
computational self-awareness, specifically reflection. By supporting these
self-awareness properties, the system can reason about the actions it takes by
considering the significance of competing objectives, user requirements, and
operating conditions while executing unpredictable workloads
Speculative Segmented Sum for Sparse Matrix-Vector Multiplication on Heterogeneous Processors
Sparse matrix-vector multiplication (SpMV) is a central building block for
scientific software and graph applications. Recently, heterogeneous processors
composed of different types of cores attracted much attention because of their
flexible core configuration and high energy efficiency. In this paper, we
propose a compressed sparse row (CSR) format based SpMV algorithm utilizing
both types of cores in a CPU-GPU heterogeneous processor. We first
speculatively execute segmented sum operations on the GPU part of a
heterogeneous processor and generate a possibly incorrect results. Then the CPU
part of the same chip is triggered to re-arrange the predicted partial sums for
a correct resulting vector. On three heterogeneous processors from Intel, AMD
and nVidia, using 20 sparse matrices as a benchmark suite, the experimental
results show that our method obtains significant performance improvement over
the best existing CSR-based SpMV algorithms. The source code of this work is
downloadable at https://github.com/bhSPARSE/Benchmark_SpMV_using_CSRComment: 22 pages, 8 figures, Published at Parallel Computing (PARCO
Planificación consciente de la contención y gestión de recursos en arquitecturas multicore emergentes
Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadores y Automática, leÃda el 14-12-2021Chip multicore processors (CMPs) currently constitute the architecture of choice for mosto general-pùrpose computing systems, and they will likely continue to be dominant in the near future. Advances in technology have enabled to pack an increasing number of cores and bigger caches on the same chip. Nevertheless, contention on shared resources on CMPs -present since the advent of these architectures- still poses a big challenge. Cores in a CMP typically share a last-level cache (LLC) and other memory-related resources with the remaining cores, such as a DRAM controller and an interconnection network. This causes that co-running applications may intensively compete with each other for these shared resources, leading to substantial and uneven performance degradation...Los procesadores multinúcleo o CMPs (Chip Multicore Processors) son actualmente la arquitectura más usada por la mayorÃa de sistemas de computación de propósito
general, y muy probablemente se mantendrÃan en esa posición dominante en el futuro cercano. Los avances tecnológicos han permitido integrar progresivamente en el mismo chip más cores y aumentar los tamaños de los distintos niveles de
cache. No obstante, la contención de recursos compartidos en CMPs {presente desde la aparición de estas arquitecturas{ todavÃa representa un reto importante que afrontar. Los cores en un CMP comparten en la mayor parte de los diseños
una cache de último nivel o LLC (Last-Level Cache) y otros recursos, como el controlador de DRAM o una red de interconexión. La existencia de dichos recursos compartidos provoca en ocasiones que cuando se ejecutan dos o más aplicaciones simultáneamente en el sistema, se produzca una degradación sustancial y potencialmente desigual del rendimiento entre aplicaciones...Fac. de InformáticaTRUEunpu
Investigation into scalable energy and performance models for many-core systems
PhD ThesisIt is likely that many-core processor systems will continue to penetrate
emerging embedded and high-performance applications. Scalable energy and
performance models are two critical aspects that provide insights into the
conflicting trade-offs between them with growing hardware and software
complexity. Traditional performance models, such as Amdahl’s Law,
Gustafson’s and Sun-Ni’s, have helped the research community and industry
to better understand the system performance bounds with given processing
resources, which is otherwise known as speedup. However, these models and
their existing extensions have limited applicability for energy and/or
performance-driven system optimization in practical systems. For instance,
these are typically based on software characteristics, assuming ideal and
homogeneous hardware platforms or limited forms of processor
heterogeneity. In addition, the measurement of speedup and parallelization
factors of an application running on a specific hardware platform require
instrumenting the original software codes. Indeed, practical speedup and
parallelizability models of application workloads running on modern
heterogeneous hardware are critical for energy and performance models, as
they can be used to inform design and control decisions with an aim to
improve system throughput and energy efficiency.
This thesis addresses the limitations by firstly developing novel and
scalable speedup and energy consumption models based on a more general
representation of heterogeneity, referred to as the normal form heterogeneity.
A method is developed whereby standard performance counters found in
modern many-core platforms can be used to derive speedup, and therefore
the parallelizability of the software, without instrumenting applications. This
extends the usability of the new models to scenarios where the
parallelizability of software is unknown, leading to potentially Run-Time
Management (RTM) speedup and/or energy efficiency optimization. The
models and optimization methods presented in this thesis are validated
through extensive experimentation, by running a number of different
applications in wide-ranging concurrency scenarios on a number of different
homogeneous and heterogeneous Multi/Many Core Processor (M/MCP)
systems. These include homogeneous and heterogeneous architectures and
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range from existing off-the-shelf platforms to potential future system
extensions. The practical use of these models and methods is demonstrated
through real examples such as studying the effectiveness of the system load
balancer.
The models and methodologies proposed in this thesis provide guidance to
a new opportunities for improving the energy efficiency of M/MCP systemsHigher Committee of Education Development
(HCED) in Ira
Mapping parallelism to heterogeneous processors
Most embedded devices are based on heterogeneous Multiprocessor System on Chips
(MPSoCs). These contain a variety of processors like CPUs, micro-controllers, DSPs,
GPUs and specialised accelerators. The heterogeneity of these systems helps in achieving
good performance and energy efficiency but makes programming inherently difficult.
There is no single programming language or runtime to program such platforms.
This thesis makes three contributions to these problems. First, it presents a framework
that allows code in Single Program Multiple Data (SPMD) form to be mapped
to a heterogeneous platform. The mapping space is explored, and it is shown that the
best mapping depends on the metric used.
Next, a compiler framework is presented which bridges the gap between the high
-level programming model of OpenMP and the heterogeneous resources of MPSoCs.
It takes OpenMP programs and generates code which runs on all processors. It delivers
programming ease while exploiting heterogeneous resources.
Finally, a compiler-based approach to runtime power management for heterogeneous
cores is presented. Given an externally provided budget, the approach generates
heterogeneous, partitioned code that attempts to give the best performance within that
budget
Castell: a heterogeneous cmp architecture scalable to hundreds of processors
Technology improvements and power constrains have taken multicore architectures to dominate
microprocessor designs over uniprocessors. At the same time, accelerator based architectures
have shown that heterogeneous multicores are very efficient and can provide high throughput for
parallel applications, but with a high-programming effort. We propose Castell a scalable chip
multiprocessor architecture that can be programmed as uniprocessors, and provides the high
throughput of accelerator-based architectures.
Castell relies on task-based programming models that simplify software development. These
models use a runtime system that dynamically finds, schedules, and adds hardware-specific features
to parallel tasks. One of these features is DMA transfers to overlap computation and data
movement, which is known as double buffering. This feature allows applications on Castell
to tolerate large memory latencies and lets us design the memory system focusing on memory
bandwidth.
In addition to provide programmability and the design of the memory system, we have used
a hierarchical NoC and added a synchronization module. The NoC design distributes memory
traffic efficiently to allow the architecture to scale. The synchronization module is a consequence
of the large performance degradation of application for large synchronization latencies.
Castell is mainly an architecture framework that enables the definition of domain-specific
implementations, fine-tuned to a particular problem or application. So far, Castell has been
successfully used to propose heterogeneous multicore architectures for scientific kernels, video
decoding (using H.264), and protein sequence alignment (using Smith-Waterman and clustalW).
It has also been used to explore a number of architecture optimizations such as enhanced DMA
controllers, and architecture support for task-based programming models.
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Multithreading Aware Hardware Prefetching for Chip Multiprocessors
To take advantage of the processing power in the Chip Multiprocessors design,
applications must be divided into semi-independent processes that can run concur-
rently on multiple cores within a system. Therefore, programmers must insert thread
synchronization semantics (i.e. locks, barriers, and condition variables) to synchro-
nize data access between processes. Indeed, threads spend long time waiting to
acquire the lock of a critical section. In addition, a processor has to stall execution
to wait for load data accesses to complete. Furthermore, there are often independent instructions which include load instructions beyond synchronization semantics that could be executed in parallel while a thread waits on the synchronization semantics. The conveniences of the cache memories come with some extra cost in Chip Multiprocessors. Cache Coherence mechanisms address the Memory Consistency problem. However, Cache Coherence adds considerable overhead to memory accesses. Having aggressive prefetcher on different cores of a Chip Multiprocessor can definitely lead to significant system performance degradation when running multi-threaded applications. This result of prefetch-demand interference when a prefetcher in one core ends up pulling shared data from a producing core before it has been written, the cache block will end up transitioning back and forth between the cores and result in useless prefetch, saturating the memory bandwidth and substantially increase the latency to critical shared data.
We present a hardware prefetcher that enables large performance improvements
from prefetching in Chip Multiprocessors by significantly reducing prefetch-demand
interference. Furthermore, it will utilize the time that a thread spends waiting on syn-
chronization semantics to run ahead of the critical section to speculate and prefetch independent load instruction data beyond the synchronization semantics
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