A 192×128 Time Correlated SPAD Image Sensor in 40-nm CMOS Technology

A 192 X 128 pixel single photon avalanche diode (SPAD) time-resolved single photon counting (TCSPC) image sensor is implemented in STMicroelectronics 40-nm CMOS technology. The 13% fill factor, 18.4\,\,\mu \text {m} \times 9.2\,\,\mu \text{m} pixel contains a 33-ps resolution, 135-ns full scale, 12-bit time-to-digital converter (TDC) with 0.9-LSB differential and 5.64-LSB integral nonlinearity (DNL/INL). The sensor achieves a mean 219-ps full-width half-maximum (FWHM) impulse response function (IRF) and is operable at up to 18.6 kframes/s through 64 parallelized serial outputs. Cylindrical microlenses with a concentration factor of 3.25 increase the fill factor to 42%. The median dark count rate (DCR) is 25 Hz at 1.5-V excess bias. A digital calibration scheme integrated into a column of the imager allows off-chip digital process, voltage, and temperature (PVT) compensation of every frame on the fly. Fluorescence lifetime imaging microscopy (FLIM) results are presented

Photon Counting and Direct ToF Camera Prototype Based on CMOS SPADs

This paper presents a camera prototype for 2D/3D image capture in low illumination conditions based on single-photon avalanche-diode (SPAD) image sensor for direct time-offlight (d-ToF). The imager is a 64×64 array with in-pixel TDC for high frame rate acquisition. Circuit design techniques are combined to ensure successful 3D image capturing under low sensitivity conditions and high level of uncorrelated noise such as dark count and background illumination. Among them an innovative time gated front-end for the SPAD detector, a reverse start-stop scheme and real-time image reconstruction at Ikfps are incorporated by the imager. To the best of our knowledge, this is the first ToF camera based on a SPAD sensor fabricated and proved for 3D image reconstruction in a standard CMOS process without any opto-flavor or high voltage option. It has a depth resolution of 1cm at an illumination power from less than 6nW/mm 2 down to 0.1nW/mm 2 .Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad TEC2015-66878-C3- 1-RJunta de Andalucía P12-TIC 233

Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors

Direct time-of-flight (d-ToF) estimation with high frame rate requires the incorporation of a time-to-digital converter (TDC) at pixel level. A feasible approach to a compact implementation of the TDC is to use the multiple phases of a voltage-controlled ring-oscillator (VCRO) for the finest bits. The VCRO becomes central in determining the performance parameters of a d-ToF image sensor. In this paper, we are covering the modeling, design, and measurement of a CMOS pseudo-differential VCRO. The oscillation frequency, the jitter due to mismatches and noise and the power consumption are analytically evaluated. This design has been incorporated into a 64x64-pixel array. It has been fabricated in a 0.18 mu m standard CMOS technology. Occupation area is 28x29 mu m(2) and power consumption is 1.17 mW at 850 MHz. The measured gain of the VCRO is of 477 MHz/V with a frequency tuning range of 53%. Moreover, it features a linearity of 99.4% over a wide range of control frequencies, namely, from 400 to 850 MHz. The phase noise is of -102 dBc/Hz at 2 MHz offset frequency from 850 MHz. The influence of these parameters in the performance of the TDC has been measured. The minimum time bin of the TDC is 147 ps with a rms DNL/INL of 0.13/1.7LSB.Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad TEC2015-66878-C3-1-RJunta de Andalucía P12-TIC 233

In-pixel Voltage-Controlled Ring-Oscillator for Phase Interpolation in ToF Image Sensors

The design and measurements of a CMOS pseudodifferential voltage-controlled ring-oscillator (VCRO) are presented. It is aimed to act as time interpolator for arrayable picosecond time-to-digital convertors (TDC). This design is incorporated into a 64×64 array of TDCs for time-of-flight (ToF) measurement. It has been fabricated in a 0.18μm standard CMOS technology. Small occupation area of 28×29μm2 and low average power consumption of 1.17mW at 850MHz are promising figures for this application field. Embedded phase alignment and instantaneous start-up time are required to minimize the offset of time interval measurements. The measured gain of the VCRO is of 477MHz/V with a frequency tuning range of 53%. Moreover it features a linearity of 99.4% over a wide range of control frequencies, namely from 400MHz to 850MHz. The phase noise is of 102dBc/Hz at 2MHz offset frequency from 850MHz.Junta de Andalucía, Consejería de Economía, Innovación, Ciencia y Empleo (CEICE) TIC 2012- 233

Time-to-digital converters and histogram builders in SPAD arrays for pulsed-LiDAR

Light Detection and Ranging (LiDAR) is a 3D imaging technique widely used in many applications such as augmented reality, automotive, machine vision, spacecraft navigation and landing. Pulsed-LiDAR is one of the most diffused LiDAR techniques which relies on the measurement of the round-trip travel time of an optical pulse back-scattered from a distant target. Besides the light source and the detector, Time-to-Digital Converters (TDCs) are fundamental components in pulsed-LiDAR systems, since they allow to measure the back-scattered photon arrival times and their performance directly impact on LiDAR system requirements (i.e., range, precision, and measurements rate). In this work, we present a review of recent TDC architectures suitable to be integrated in SPAD-based CMOS arrays and a review of data processing solutions to derive the TOF information. Furthermore, main TDC parameters and processing techniques are described and analyzed considering pulsed-LiDAR requirements

Strategies towards high performance (high-resolution/linearity) time-to-digital converters on field-programmable gate arrays

Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility, and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required.Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility, and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required

Time resolved single photon imaging in Nanometer Scale CMOS technology

Time resolved imaging is concerned with the measurement of photon arrival time. It has a wealth of emerging applications including biomedical uses such as fluorescence lifetime microscopy and positron emission tomography, as well as laser ranging and imaging in three dimensions. The impact of time resolved imaging on human life is significant: it can be used to identify cancerous cells in-vivo, how well new drugs may perform, or to guide a robot around a factory or hospital. Two essential building blocks of a time resolved imaging system are a photon detector capable of sensing single photons, and fast time resolvers that can measure the time of flight of light to picosecond resolution. In order to address these emerging applications, miniaturised, single-chip, integrated arrays of photon detectors and time resolvers must be developed with state of the art performance and low cost. The goal of this research is therefore the design, layout and verification of arrays of low noise Single Photon Avalanche Diodes (SPADs) together with high resolution Time-Digital Converters (TDCs) using an advanced silicon fabrication process. The research reported in this Thesis was carried out as part of the E.U. funded Megaframe FP6 Project. A 32x32 pixel, one million frames per second, time correlated imaging device has been designed, simulated and fabricated using a 130nm CMOS Imaging process from ST Microelectronics. The imager array has been implemented together with required support cells in order to transmit data off chip at high speed as well as providing a means of device control, test and calibration. The fabricated imaging device successfully demonstrates the research objectives. The Thesis presents details of design, simulation and characterisation results of the elements of the Megaframe device which were the author’s own work. Highlights of the results include the smallest and lowest noise SPAD devices yet published for this class of fabrication process and an imaging array capable of recording single photon arrivals every microsecond, with a minimum time resolution of fifty picoseconds and single bit linearity

Injection locked ring oscillator design for application in Direct Time of Flight LIDAR

Diplomová práce přibližuje systémy LIDAR přímo měřící čas průletu a časově digitální převodníky určené k použití v těchto systémech. Představuje problematiku distribuce hodinových signálů napříč soubory časově digitálních převodníků v LIDAR systémech a věnuje se jednomu z nových řešení této problematiky, které je založené na injekcí zavěšených oscilátorech. Technika injekčního zavěšení oscilátorů je důkladně matematicky popsána. V programu Matlab byl vytvořen simulační model injekcí zavěšeného kruhového oscilátoru, který potvrzuje správnost uvedených analytických predikcí. Ve výrobní technologii ONK65 byl navržen injekcí zavěšený kruhový oscilátor stabilizovaný pomocí smyčky závěsu zpoždění, určený pro implementaci časově digitálního převodníku pro systém LIDAR. Navržený injekcí zavěšený kruhový oscilátor byl verifikován počítačovými simulacemi zohledňujícími vliv procesních, napěťových i teplotních variací. Oscilátor poskytuje specifikované časové rozlišení 50 pikosekund a dosahuje dvakrát nižší hodnoty fázového neklidu než ekvivalentní volnoběžný oscilátor v dané technologii.The diploma thesis provides an introduction to Direct Time of Flight LIDAR systems and Time to Digital Converters used in these systems. It discusses the problem of clock distribution in LIDAR Time to Digital Converter arrays, and examines one of the possible solutions to this problem based on injection locked oscillators. The injection locking phenomenon is thoroughly mathematically described and a Matlab model of an injection locked ring oscillator is presented, confirming the analytic predictions. In ONK65 processing technology, an injection locked ring oscillator biased by a delay locked loop meant specifically for application in Time to Digital Converters for LIDAR systems has been designed. The designed oscillator has been verified by computer simulations taking process, voltage and temperature variations into account and offers specified time resolution of 50 picosecond as well as two times less clock jitter than an equivalent free-running oscillator in the given processing technology.

Électronique d’un convertisseur photon-numérique 3D pour une résolution temporelle de 10 ps FWHM

Les technologies utilisant la détection monophotonique sont de plus en plus présentes dans nos vies. De nombreuses applications nécessitent un photodétecteur possédant une haute efficacité de détection ainsi que d’excellentes performances temporelles, de l’ordre de 10 ps LMH. L’un des exemples qui aura un impact dans nos vies à court terme est l’intégration de système de télémétrie laser sur les véhicules afin de les rendre autonomes. Le domaine de l’imagerie médicale peut également profiter du développement de nouveaux photodétecteurs possédant une très haute précision temporelle. Par exemple, la tomographie d’émission par positrons permet d’imager le métabolisme des cellules, une technique très utilisée dans la détection de tumeurs cancéreuses. Une résolution temporelle en coïncidence de 10 ps LMH permet d’augmenter drastiquement le contraste des images des scanners TEP en localisant l’endroit sur la ligne de réponse où s’est produite l’annihilation du positron et de l’électron. L’atteinte d’une résolution de 10 ps LMH représenterait un changement de paradigme puisqu’il serait possible de produire directement une image sans utiliser un processus de reconstruction. Présentement, les cristaux scintillateurs et les photodétecteurs sont les deux facteurs limitant l’atteinte d’une résolution de 10 ps LMH. Au niveau du photodétecteur, une gigue temporelle de détection de photon unique de 10 ps LMH est requise pour atteindre une résolution en coïncidence de 10 ps LMH. Le Groupe de recherche en appareillage médicale travaille à atteindre cette performance depuis de nombreuses années. Le projet phare du groupe au niveau du développement de photodétecteur est le convertisseur photon-numérique 3D. Pour ce détecteur, une intégration verticale 3D de deux puces de silicium est requise. Sur la première couche, une matrice de photodiode à avalanche monophotonique est conçue dans une technologie sur mesure de Teledyne Dalsa Semiconductor Inc est intégrée en 3D sur une seconde couche de technologie standard CMOS 65 nm de Taiwan Semiconductor Manufacturing Company ltd. Ce projet de doctorat vise à concevoir un circuit en technologie CMOS qui attribue à chaque photodiode à avalanche monophotonique un circuit d’étouffement et un convertisseur temps-numérique possédant une gigue sous les 10 ps LMH. Cette thèse présente le développement d’une matrice de 256 circuits de lecture de photodiodes à avalanche monophotonique optimisés pour obtenir la meilleure résolution temporelle tout en intégrant un circuit de traitement numérique. Pour atteindre une résolution de 10 ps LMH, un système de correction des non-uniformités et des variations de délai de propagation de chaque pixel a été implémenté. Pour finir, cette recherche conclut sur l’implémentation d’un circuit d’asservissement pour stabiliser les performances du convertisseur temps-numérique pour les variations de tension d’alimentations et de température

CMOS Sensors for Time-Resolved Active Imaging

In the past decades, time-resolved imaging such as fluorescence lifetime or time-of-flight depth imaging has been extensively explored in biomedical and industrial fields because of its non-invasive characterization of material properties and remote sensing capability. Many studies have shown its potential and effectiveness in applications such as cancer detection and tissue diagnoses from fluorescence lifetime imaging, and gesture/motion sensing and geometry sensing from time-of-flight imaging. Nonetheless, time-resolved imaging has not been widely adopted due to the high cost of the system and performance limits. The research presented in this thesis focuses on the implementation of low-cost real-time time-resolved imaging systems. Two image sensing schemes are proposed and implemented to address the major limitations. First, we propose a single-shot fluorescence lifetime image sensors for high speed and high accuracy imaging. To achieve high accuracy, previous approaches repeat the measurement for multiple sampling, resulting in long measurement time. On the other hand, the proposed method achieves both high speed and accuracy at the same time by employing a pixel-level processor that takes and compresses the multiple samples within a single measurement time. The pixels in the sensor take multiple samples from the fluorescent optical signal in sub-nanosecond resolution and compute the average photon arrival time of the optical signal. Thanks to the multiple sampling of the signal, the measurement is insensitive to the shape or the pulse-width of excitation, providing better accuracy and pixel uniformity than conventional rapid lifetime determination (RLD) methods. The proposed single-shot image sensor also improves the imaging speed by orders of magnitude compared to other conventional center-of-mass methods (CMM). Second, we propose a 3-D camera with a background light suppression scheme which is adaptable to various lighting conditions. Previous 3-D cameras are not operable in outdoor conditions because they suffer from measurement errors and saturation problems under high background light illumination. We propose a reconfigurable architecture with column-parallel discrete-time background light cancellation circuit. Implementing the processor at the column level allows an order of magnitude reduction in pixel size as compared to existing pixel-level processors. The column-level approach also provides reconfigurable operation modes for optimal performance in all lighting conditions. For example, the sensor can operate at the best frame-rate and resolution without the presence of background light. If the background light saturates the sensor or increases the shot noise, the sensor can adjust the resolution and frame-rate by pixel binning and superresolution techniques. This effectively enhances the well capacity of the pixel to compensate for the increase shot noise, and speeds up the frame processing to handle the excessive background light. A fabricated prototype sensor can suppress the background light more than 100-klx while achieving a very small pixel size of 5.9μm.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/136950/1/eecho_1.pd