Devenlopment of Compact Small Signal Quasi Static Models for Multiple Gate Mosfets

En esta tesis hemos desarrollado los modelos compactos explícitos de carga y de capacitancia adaptados para los dispositivos dopados y no dopados de canal largo (DG MOSFETs dopados, DG MOSFETs no dopados, UTB MOSFETs no dopados y SGT no dopados) de un modelo unificado del control de carga derivado de la ecuación de Poisson. El esquema de modelado es similar en todos estos dispositivos y se adapta a cada geometría. Los modelos de la C.C. y de la carga son completamente compatibles. Las expresiones de la capacitancia se derivan del modelo de la carga. La corriente, la carga total y las capacitancias se escriben en términos de las densidades móviles de la carga en los extremos de fuente y drenador del canal. Las expresiones explícitas e infinitamente continuas se utilizan para las densidades móviles de la carga en la fuente y drenador. Las capacitancias modeladas demuestran el acuerdo excelente con las simulaciones numéricas 2D y 3D (SGT), en todos los regímenes de funcionamiento. Por lo tanto, el modelo es muy prometedor para ser utilizado en simuladores del circuito. Desafortunadamente, no mucho trabajo se ha dedicado a este dominio de modelado. Las cargas analíticas y las capacitancias, asociadas a cada terminal se prefieren en la simulación de circuito. Con respecto al SGT MOSFET, nuestro grupo fue el primero en desarrollar y publicar un modelo de las cargas y de las capacitancias intrínsecas, que es también analítico y explícito. La tesis es organizada como sigue: el capítulo (1) presenta el estado del arte, capítulo (2) el modelado compacto de los cuatro dispositivos: DG MOSFETs dopados, DG MOSFETs no dopados, UTB MOSFETs no dopados y SGT no dopados; en el capítulo (3) estudiamos las capacitancias de fricción en MuGFETs. Finalmente el capítulo (4) resuma el trabajo hecho y los futuros objetivos que necesitan ser estudiados. Debido a la limitación de los dispositivos optimizados disponibles para el análisis, la simulación numérica fue utilizada como la herramienta principal del análisis. Sin embargo, cuando estaban disponibles, medidas experimentales fueron utilizadas para validar nuestros resultados. Por ejemplo, en la sección 2A, en el caso de DG MOSFETs altamente dopados podríamos comparar nuestros resultados con datos experimentales de FinFETs modelados como DG MOSFETs. La ventaja principal de este trabajo es el carácter analítico y explícito del modelo de la carga y de la capacitancia que las hace fácil de implementar en simuladores de circuitos. El modelo presenta los resultados casi perfectos para diversos casos del dopaje y para diversas estructuras no clásicas del MOSFET (los DG MOSFETs, los UTB MOSFETs y los SGTs). La variedad de las estructuras del MOSFET en las cuales se ha incluido nuestro esquema de modelado y los resultados obtenidos, demuestran su validez absoluta. En el capítulo 3, investigamos la influencia de los parámetros geométricos en el funcionamiento en RF de los MuGFETs. Demostramos el impacto de parámetros geométricos importantes tales como el grosor de la fuente y del drenador o, el espaciamiento de las fins, la anchura del espaciador, etc. en el componente parásito de la capacitancia de fricción de los transistores de la múltiple-puerta (MuGFET). Los resultados destacan la ventaja de disminuir el espaciamiento entre las fins para MuGFETs y la compensación entre la reducción de las resistencias parásitas de fuente y drenador y el aumento de capacitancias de fricción cuando se introduce la tecnología del crecimiento selectivo epitaxial (SEG). La meta de nuestro estudio y trabajo es el uso de nuestros modelos en simuladores de circuitos. El grupo de profesor Aranda, de la Universidad de Granada ha puesto el modelo actual de SGT en ejecución en el simulador Agilent ADS y buenos resultados fueron obtenidos.In this thesis we have developed explicit compact charge and capacitance models adapted for doped and undoped long-channel devices (doped Double-Gate (DG) MOSFETs, undoped DG MOSFETs, undoped Ultra-Thin-Body (UTB) MOSFETs and undoped Surrounding Gate Transistor (SGT)) from a unified charge control model derived from Poisson's equation. The modelling scheme is similar in all these devices and is adapted to each geometry. The dc and charge models are fully compatible. The capacitance expressions are derived from the charge model. The current, total charges and capacitances are written in terms of the mobile charge sheet densities at the source and drain ends of the channel. Explicit and infinitely continuous expressions are used for the mobile charge sheet densities at source and drain. As a result, all small signal parameters will have an infinite order of continuity. The modeled capacitances show excellent agreement with the 2D and 3D (SGT) numerical simulations, in all operating regimes. Therefore, the model is very promising for being used in circuit simulators. Unfortunately, not so much work has been dedicated to this modelling domain. Analytical charges and capacitances, associated with each terminal are preferred in circuit simulation. Regarding the surrounding-gate MOSFET, our group was the first to develop and publish a model of the charges and intrinsic capacitances, which is also analytic and explicit. The thesis is organized as follows: Chapter (1) presents the state of the art, Chapter (2) the compact modeling of the four devices: doped DG MOSFETs, undoped DG MOSFETs, undoped UTB MOSFETs and undoped SGT; in Chapter (3) we study the fringing capacitances in MuGFETs. Finally Chapter (4) summarizes the work done and the future points that need to be studied. Due to the limitation of available optimized devices for analysis, numerical simulation was used as the main analysis tool. However, when available, measurements were used to validate our results. The experimental part was realised at the Microelectronics Laboratory, Université Catholique de Louvain, Louvain-la Neuve, Belgium. For example, in section 2A, in the case of highly-doped DG MOSFETs we could compare our results with experimental data from FinFETs modeled as DG MOSFETs. The main advantage of this work is the analytical and explicit character of the charge and capacitance model that makes it easy to implement in circuit simulators. The model presents almost perfect results for different cases of doping (doped/undoped devices) and for different non classical MOSFET structures (DG MOSFET, UTB MOSFETs and SGT). The variety of the MOSFET structures in which our modeling scheme has been included and the obtained results, demonstrate its absolute validity. In chapter 3, we investigate the influence of geometrical parameters on the RF performance in MuGFETs. We show the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET). Results highlight the advantage of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The goal of our study and work is the usage of our models in circuit simulators. This part, of implementing and testing our models of these multi gate MOSFET devices in circuit simulators has already begun. The group of Professor Aranda, from the University of Granada has implemented the SGT current model in the circuit simulator Agilent ADS and good results were obtained

Two-Dimensional Analytical Modeling of Tunnel-FETs

Basat en un mecanisme de transport de corrent de banda a banda, el túnel-FET és capaç de superar la limitació de pendent sub-llindar física del MOSFET de 60 mV /dec. Per tant, s'ha convertit en un dels dispositius més prometedors per ser el successor del MOSFET clàssic en els últims anys. Aquesta tesi descriu tots els passos necessaris per modelar analíticament un Túnel-FET de doble porta. El model inclou una solució electrostàtica de dues dimensions en totes les regions del dispositiu, el que permet fins i tot simulacions hetero-unió del dispositiu. Per a un comportament més realista del dispositiu, cal tenir en compte el rendiment del dispositiu que limita els perfils de dopatge de forma Gaussiana en les unions del canal. Les expressions per a les probabilitats de túnel de banda a banda i les de Trap-Assisted-Tunneling (TAT) són executades per un enfocament WKB quasi bidimensional. El corrent del dispositiu es calcula mitjançant la teoria de transmissió de Landauer. El model és vàlid per a dispositius de canal curt i les estàncies estan ben comparades amb les dades de simulació TCAD Sentaurus i amb les medicions proporcionades. S'introdueix un modelo general per les flactuacions del dopant aleatoria, que prediu les influencies característiques del dispositiu en el corrent de sortida i el voltatge llindar. El model s'aplica al MOSFET, així com a dispositius TFET.Basado en un mecanismo de transporte de corriente banda a banda, el Tunnel-FET es capaz de superar la limitación de pendiente sub-umbral física del MOSFET de 60 mV/dec. Por lo tanto, esto lo convierte en uno de los dispositivos más prometedores para ser el sucesor del MOSFET clásico en los últimos años. Esta tesis describe todos los pasos necesarios para modelar analíticamente un Tunnel-FET de doble puerta. El modelo incluye una solución electrostática bidimensional en todas las regiones del dispositivo, lo que permite incluso simulaciones de hetero-unión del dispositivo. Para un comportamiento más realista del dispositivo se tiene en cuenta el rendimiento del dispositivo que limita los perfiles de dopaje de forma Gaussiana en las uniones del canal. Las expresiones para las probabilidades de túnel de banda a banda y de Trap-Assisted-Tunneling (TAT) se implementan mediante un enfoque de WKB cuasi bidimensional. La corriente del dispositivo se calcula mediante la teoría de transmisión de Landauer. El modelo es válido para dispositivos de canal corto y las estancias están bien comparadas con los datos de simulación TCAD Sentaurus y con las mediciones proporcionadas. Se introduce un modelo general para las fluctuaciones del dopado aleatorio, que predice las influencias características del dispositivo en la corriente de salida y el voltaje umbral. El modelo se aplica al MOSFET, así como a los dispositivos TFET.Based on a band-to-band current transport mechanism, the Tunnel-FET is able to overcome the physical subthreshold slope limitation of the MOSFET of 60 mV/dec. Therefore, it has become one of the most promising devices to be the successor of the classical MOSFET in the last few years. This thesis describes all necessary steps to analytically model a double-gate Tunnel-FET. The model includes a two-dimensional electrostatic solution in all device regions, which enables even hetero-junction device simulations. Device performance limiting Gaussian-shaped doping profiles at the channel junctions are taken into account for a realistic device behavior. Expressions for the band-to-band and trap-assisted-tunneling probabilities are implemented by a quasi two-dimensional WKB approach. The device current is calculated based on Landauer's transmission theory. The model is valid for short-channel devices and stays is good agreement with the TCAD Sentaurus simulation data and with the provided measurements. A general model for random-dopant-fluctuations is introduced, which predicts characteristic device influences on the output current and threshold voltage. The model is applied to MOSFET, as well as TFET devices

Modeling & Performance Enhancement Analysis of Some Nanoscale MOSFET Structures

Silicon-on-Insulator (SOI) has been the forerunner of the CMOS technology in the last few decades offering superior CMOS devices with higher speed, higher density and reduced second order effects for submicron VLSI applications. Recent experimental studies invigorated interest in Fully Depleted (FD) SOI devices because of their potentially superior scalability relative to bulk silicon CMOS devices. Various new structures with different engineering concepts have been reported to reduce the SCEs in SOI platform. Among them Strain engineering and high-k gate dielectric with metal gate technology are very popular for enhancing the carrier mobility and reduction of gate leakage current. In this thesis, first physics based 2-D model for surface potential, threshold voltage and electric field for a Fully Depleted Strained Silicon on Insulator (FD-S-SOI) MOSFET by solving the two dimensional Poisson’s equation is presented. The model details the role of various MOS parameters like germanium concentration, body doping concentration, strained silicon thickness, oxide thickness and gate metal work function influencing the surface potential, threshold voltage and electric field. Then extensive numerical simulation is done to study the effect of device design engineering on the analog/RF performance of nanoscale DGMOSFET by varying the gate work function, channel length and gate oxide. Including the Short Channel Effects (SCEs) the important analog/RF figures of merit (FOMs) are also examined. Finally one optimum device is presented with great immunization to SCEs and highly applicable to analog/RF applications

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

Investigation on Performance Metrics of Nanoscale Multigate MOSFETs towards RF and IC Applications

Silicon-on-Insulator (SOI) MOSFETs have been the primary precursor for the CMOS technology since last few decades offering superior device performance in terms of package density, speed, and reduced second order harmonics. Recent trends of investigation have stimulated the interest in Fully Depleted (FD) SOI MOSFET because of their remarkable scalability efficiency. However, some serious issues like short channel effects (SCEs) viz drain induced barrier lowering (DIBL), Vth roll-off, subthreshold slope (SS), and hot carrier effects (HCEs) are observed in nanoscale regime. Numerous advanced structures with various engineering concepts have been addressed to reduce the above mentioned SCEs in SOI platform. Among them strain engineering, high-k gate dielectric with metal gate technology (HKMG), and non-classical multigate technologies are most popular models for enhancement in carrier mobility, suppression of gate leakage current, and better immunization to SCEs. In this thesis, the performance of various emerging device designs are analyzed in nanoscale with 2-D modeling as well as through calibrated TCAD simulation. These attempts are made to reduce certain limitations of nanoscale design and to provide a significant contribution in terms of improved performances of the miniaturized devices. Various MOS parameters like gate work function (_m), channel length (L), channel thickness (tSi), and gate oxide thickness (tox) are optimized for both FD-SOI and Multiple gate technology. As the semiconductor industries migrate towards multigate technology for system-on-chip (SoC), system-in-package (SiP), and internet-of-things (IoT) applications, an appropriate examination of the advanced multiple gate MOFETs is required for the analog/RF application keeping reliability issue in mind. Various non-classical device structures like gate stack engineering and halo doping in the channel are extensively studied for analog/RF applications in double gate (DG) platform. A unique attempt has been made for detailed analysis of the state-of-the-art 3-D FinFET on dependency of process variability. The 3-D architecture is branched as Planar or Trigate or FinFET according to the aspect ratio (WFin=HFin). The evaluation of zero temperature coefficient (ZTC) or temperature inflection point (TCP) is one of the key investigation of the thesis for optimal device operation and reliability. The sensitivity of DG-MOSFET and FinFET performances have been addressed towards a wide range of temperature variations, and the ZTC points are identified for both the architectures. From the presented outcomes of this work, some ideas have also been left for the researchers for design of optimum and reliable device architectures to meet the requirements of high performance (HP) and/or low standby power (LSTP) applications

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

Intrinsic variability of nanoscale CMOS technology for logic and memory.

The continuous downscaling of CMOS technology, the main engine of development of the semiconductor Industry, is limited by factors that become important for nanoscale device size, which undermine proper device operation completely offset gains from scaling. One of the main problems is device variability: nominally identical devices are different at the microscopic level due to fabrication tolerance and the intrinsic granularity of matter. For this reason, structures, devices and materials for the next technology nodes will be chosen for their robustness to process variability, in agreement with the ITRS (International Technology Roadmap for Semiconductors). Examining the dispersion of various physical and geometrical parameters and the effect these have on device performance becomes necessary. In this thesis, I focus on the study of the dispersion of the threshold voltage due to intrinsic variability in nanoscale CMOS technology for logic and for memory. In order to describe this, it is convenient to have an analytical model that allows, with the assistance of a small number of simulations, to calculate the standard deviation of the threshold voltage due to the various contributions

Journal of Telecommunications and Information Technology, 2004, nr 1

kwartalni

Compact Modeling of Intrinsic Capacitances in Double-Gate Tunnel-FETs

La miniaturització dels MOSFET en els circuits integrats ha elevat la tecnologia microelectrònica. Aquesta tendència també augmenta el grau de complexitat d'aquests circuits i els seus components bàsics. En els MOSFET convencionals, el corrent es basa en l'emissió termoiònica de portadors de càrrega, que per això limita el pendent subumbral en aquests transistors a 60 mV / dec. Per tant, per superar aquest límit i continuar amb la miniaturització per mantenir el ritme de la llei de Moore, es requereixen estructures alternatives. Entre aquestes, el transistor d'efecte de camp per túnel (TFET) es considera un possible successor de l'MOSFET. A causa del seu mecanisme alternatiu de transport de corrent, conegut com a túnel de banda a banda (B2B), el pendent subumbral en TFET pot fer-se inferior al límit de 60 mV / dec. Per comprendre i estimar el comportament dels TFET, no només com un element únic sinó també a nivell de circuit, es requereix un model compacte d'aquest dispositiu. En aquesta tesi es presenta un model basat en càrrega per descriure el comportament capacitiu d'un TFET de doble porta (DG TFET). No obstant això, la simplicitat i la flexibilitat de el model permeten usar-lo per a un altre tipus d'estructures TFET, com els TFET planars o de nanofils d'una sola porta (SG TFETs). El model és verificat amb les simulacions TCAD, així com amb mesures experimentals de TFET fabricats. El model de capacitància també inclou l'efecte dels elements paràsits. A més, en el context d'aquest treball també s'investiga la influència dels contactes de barrera Schottky en el comportament capacitiu dels TFET. Aquest model finalment es combina amb un model DC compacte existent per formar un model TFET compacte complet. A continuació, el model compacte s'implementa per a simulacions transitòries de circuits oscil·ladors d'anell basats en TFET.La miniaturización de los MOSFET en los circuitos integrados ha elevado la tecnología microelectrónica. Esta tendencia también aumenta el grado de complejidad de estos circuitos y sus componentes básicos. En los MOSFET convencionales, la corriente se basa en la emisión termoiónica de portadores de carga, que por ello limita la pendiente subumbral en estos transistores a 60 mV/dec. Por tanto, para superar este límite y continuar con la miniaturización para mantener el ritmo de la ley de Moore, se requieren estructuras alternativas. Entre estas, el transistor de efecto de campo por túnel (TFET) se considera un posible sucesor del MOSFET. Debido a su mecanismo alternativo de transporte de corriente, conocido como túnel de banda a banda (B2B), la pendiente subumbral en TFET puede hacerse inferior al límite de 60 mV/dec. Para comprender y estimar el comportamiento de los TFET, no sólo como un elemento único sino también a nivel de circuito, se requiere un modelo compacto de este dispositivo. En esta tesis se presenta un modelo basado en carga para describir el comportamiento capacitivo de un TFET de doble puerta (DG TFET). Sin embargo, la simplicidad y la flexibilidad del modelo permiten usarlo para otro tipo de estructuras TFET, como los TFET planares o de nanohílos de una sola puerta (SG TFETs). El modelo es verificado con las simulaciones TCAD, así como con medidas experimentales de TFET fabricados. El modelo de capacitancia también incluye el efecto de los elementos parásitos. Además, en el contexto de este trabajo también se investiga la influencia de los contactos de barrera Schottky en el comportamiento capacitivo de los TFET. Este modelo finalmente se combina con un modelo DC compacto existente para formar un modelo TFET compacto completo. A continuación, el modelo compacto se implementa para simulaciones transitorias de circuitos osciladores de anillo basados en TFET.Miniaturization of the MOSFETs on the integrated circuits has elevated the microelectronic technology. This trend also increases the degree of complexity of these circuits and their building blocks. In conventional MOSFETs the current is based on the thermionic—emission of charge carrier, which therefore limits the subthreshold swing in these transistors to 60 mV/dec. Hence, to overcome this limit and continue with down scaling to keep pace with the Moor’s law, alternative structures are required. Among these, the tunnel—field—effect transistor (TFET) is considered as a potential successor of the MOSFET. Due to its alternative current transport mechanism, known as band—to—band (B2B) tunneling, the subthreshold swing in TFETs can overcome the 60 mV/dec limit. In order to comprehend and estimate the behavior of TFETs, not only as a single element but also on the circuit level, a compact model of this device is required. In this dissertation a charge –based model to describes the capacitive behavior of a double—gate (DG) TFET is presented. However, simplicity and flexibility of the model allow to use it for other type of TFET structures such as single—gate (SG) planar or nanowire TFETs. The model is verified with the TCAD simulations as well as the measurement data of fabricated TFETs. The capacitance model also includes the effect of the parasitic elements. Furthermore, in the context of this work also the influence of Schottky barrier contacts on the capacitive behavior of TFETs is investigated. This model is finally combined with an existing compact DC model to form a complete compact TFET model. The compact model is then implemented for transient simulations of TFET—based inverter and ring—oscillator circuits

Design and simulation of strained-Si/strained-SiGe dual channel hetero-structure MOSFETs

With a unified physics-based model linking MOSFET performance to carrier mobility and drive current, it is shown that nearly continuous carrier mobility increase has been achieved by introduction of process-induced and global-induced strain, which has been responsible for increase in device performance commensurately with scaling. Strained silicon-germanium technology is a hot research area, explored by many different research groups for present and future CMOS technology, due to its high hole mobility and easy process integration with silicon. Several heterostructure architectures for strained Si/SiGe have been shown in the literature. A dual channel heterostructure consisting of strained Si/Si1-xGex on a relaxed SiGe buffer provides a platform for fabricating MOS transistors with high drive currents, resulting from high carrier mobility and carrier velocity, due to presence of compressively strained silicon germanium layer. This works reports the design, modeling and simulation of NMOS and PMOS transistors with a tensile strained Si channel layer and compressively strained SiGe channel layer for a 65 nm logic technology node. Since most of the recent work on development of strained Si/SiGe has been experimental in nature, developments of compact models are necessary to predict the device behavior. A unified modeling approach consisting of different physics-based models has been formulated in this work and their ability to predict the device behavior has been investigated. In addition to this, quantum mechanical simulations were performed in order to investigate and model the device behavior. High p/n-channel drive currents of 0.43 and 0.98 mA/Gm, respectively, are reported in this work. However with improved performance, ~ 10% electrostatic degradation was observed in PMOS due to buried channel device