CNTFET Based OTRA and its Application as Inverse Low Pass Filter

Operational Transresistance Amplifier (OTRA) has been a topic of great interest recently. OTRA has proved itself to be an appropriate device for the analog applications. As MOS scaling suffers from various problems, carbon nanotube field effect transistor (CNTFET) has came into light as one of the brightest alternative for FET (Field Effect Transistors) based devices. This work has introduced a new CNTFET based OTRA which is capable of realising inverse low pass filter using two OTRAs and few passive elements. CNTFET based OTRA has been designed and simulated at 10nm technology node. The working ability of the designed model has been conformed using HSPICE simulation. It is compared with conventional CMOS based OTRA. The comparative analysis has revealed improvement in various performance parameters. The paper also presents how change in number of carbon nanotube in CNTFETs in OTRA circuit affects the transresistance gain and input impedance. The optimized results are also discussed to improve transresistance gain and input impedance. The paper also dealt with the realisation of inverse low pass filter using proposed CNTFET based OTRA

A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

Applications of Graphene at Microwave Frequencies

In view to the epochal scenarios that nanotechnology discloses, nano-electronics has the potential to introduce a paradigm shift in electronic systems design similar to that of the transition from vacuum tubes to semiconductor devices. Since low dimensional (1D and 2D) nano-structured materials exhibit unprecedented electro-mechanical properties in a wide frequency range, including radio-frequencies (RF), microwave nano-electronics provides an enormous and yet widely undiscovered opportunity for the engineering community. Carbon nano-electronics is one of the main research routes of RF/microwave nano-electronics. In particular, graphene has shown proven results as an emblematic protagonist, and a real solution for a wide variety of microwave electronic devices and circuits. This paper introduces graphene properties in the microwave range, and presents a paradigm of novel graphene-based devices and applications in the microwave/RF frequency range

Comparitive study of electrical properties of carbon nano tube (CNT) and silicon nanowire (SNW) MOSFET devices

Metal oxide semiconductor field effect transistor (MOSFET) is a semiconductor device used in many electronic devices for amplification and switching electrical signals. MOSFET downscaling has been the driving force towards the technological advancement, but continuous scaling down of MOSFET causes problem of high power dissipation, high leakage current, Short Channel Effects (SCEs), excessive process variation and reliability issues. In this work, comparative study of electrical properties of carbon nanotube (CNT) and silicon nanowire (SWN) were carried out using CNT and SNW as channel materials, silicon dioxide as the gate dielectric, silicon substrate as base material. The analysis is carried out using FETTOY simulating software for oxide thickness (0.3,0.5,0.7,0.9 and 1.2nm). The results show that carbon nanotube channel material have highest transconductance (gm) of 1.00 x 10-4S, highest conductance (g4) of 4.00 x 10-6S, highest carrier injection velocity (vinj)of 5.43 x 10 5m/s, highest on current (Ion) of 59.79uA, at oxide thickness of 0.3nm when used as MOSFET device and improved short channel effects with subthreshold swing (S) of 67.79 mV/dec and drain induced barrier lowering (DIBL) of 39.67. More results such as drain current (Id) versus gate voltage ( Vg) , quantum capacitance (QC) versus gate voltage (Vg) , and average velocity of mobile electron versus gate voltage (Vg) for all devices are also investigated. Various results obtained indicate that CNT has the higher performance of decreasing gate capacitance with decrease in oxide thickness ( TOx) in deep nanometer regime. This decrease in gate capacitance is observed at a gate voltage of 0.5V and above which leads to the reduction of propagation delay, lower leakage current, low power dissipation, short channel effects (SCEs) as compared to silicon nanowire MOSFET device.KEYWORDS: Ballistic nanoscale MOSFET, Channel materials, FETTOY simulating software, Short channel effects (SCEs), Drain Induces Barrier Lowering (DIBL

Novel Ternary Logic Gates Design in Nanoelectronics

In this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is reduced considerably. In addition, ST-OR and ST-AND are generated directly instead of ST-NAND and ST-NOR. The proposed gates have a high noise margin near V_(DD)/4. The simulation results indicated that the power consumption and PDP underwent a~sharp decrease and noise margin showed a considerable increase in comparison to both one supply and two supply based designs in previous works. PDP is improved in the proposed OR, as compared to one supply and two supply based previous works about 83% and 63%, respectively. Also, a memory cell is designed using the proposed STI logic gate, which has a considerably lower static power to store logic ‘1’ and the static noise margin, as compared to other designs