760 research outputs found

    Continuous-time cascaded ΣΔ modulators for VDSL: A comparative study

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    This paper describes new cascaded continuous-time ΣΔ modulators intended to cope with very high-rate digital subscriber line specifications, i.e 12-bit resolution within a 20-MHz signal bandwidth. These modulators have been synthesized using a new methodology that is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. This method allows to place the zeroes/poles of the loop-filter transfer function in an optimal way and to reduce the number of analog components, namely, transconductors and/or amplifiers, resistors, capacitors and digital-to-analog converters. This leads to more efficient topologies in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealities. A comparison study of the synthesized architectures is done considering their sensitivity to most critical circuit error mechanisms. Time-domain behavioral simulations are shown to validate the presented approach.Ministerio de Educación y Ciencia TEC2004-01752/MI

    Design and implementation of a wideband sigma delta ADC

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    Abstract. High-speed and wideband ADCs have become increasingly important in response to the growing demand for high-speed wireless communication services. Continuous time sigma delta modulators (CTƩ∆M), well-known for their oversampling and noise shaping properties, offer a promising solution for low-power and high-speed design in wireless applications. The objective of this thesis is to design and implement a wideband CTƩ∆M for a global navigation satellite system(GNSS) receiver. The targeted modulator architecture is a 3rdorder single-bit CTƩ∆M, specifically designed to operate within a 15 MHz signal bandwidth. With an oversampling ratio of 25, the ADC’s sampling frequency is set at 768 MHz. The design goal is to achieve a theoretical signal to noise ratio (SNR) of 55 dB. This thesis focuses on the design and implementation of the CTƩ∆M, building upon the principles of a discrete time Ʃ∆ modulator, and leveraging system-level simulation and formulations. A detailed explanation of the coefficient calculation procedure specific to CTƩ∆ modulators is provided, along with a "top-down" design approach that ensures the specified requirements are met. MATLAB scripts for coefficient calculation are also included. To overcome the challenges associated with the implementation of CTƩ∆ modulators, particularly excess loop delay and clock jitter sensitivity, this thesis explores two key strategies: the introduction of a delay compensation path and the utilization of a finite impulse response (FIR) feedback DAC. By incorporating a delay compensation path, the stability of the modulator can be ensured and its noise transfer function (NTF) can be restored. Additionally, the integration of an FIR feedback DAC addresses the issue of clock jitter sensitivity, enhancing the overall performance and robustness of the CTƩ∆M. The CTƩ∆Ms employ the cascade of integrators with feed forward (CIFF) and cascade of integrators with feedforward and feedback (CIFF-B) topologies, with a particular emphasis on the CIFF-B configuration using 22nm CMOS technology node and a supply voltage of 0.8 V. Various simulations are performed to validate the modulator’s performance. The simulation results demonstrate an achievable SNR of 55 dB with a power consumption of 1.36 mW. Furthermore, the adoption of NTF zero optimization techniques enhances the SNR to 62 dB.Laajakaistaisen jatkuva-aikaisen sigma delta-AD-muuntimen suunnittelu ja toteutus. TiivistelmĂ€. Nopeat ja laajakaistaiset AD-muuntimet ovat tulleet entistĂ€ tĂ€rkeĂ€mmiksi nopeiden langattomien kommunikaatiopalvelujen kysynnĂ€n kasvaessa. Jatkuva-aikaiset sigma delta -modulaattorit (CTƩ∆M), joissa kĂ€ytetÀÀn ylinĂ€ytteistystĂ€ ja kohinanmuokkausta, tarjoavat lupaavan ratkaisun matalan tehonkulutuksen ja nopeiden langattomien sovellusten suunnitteluun. TĂ€mĂ€n työn tarkoituksena on suunnitella ja toteuttaa laajakaistainen jatkuva -aikainen sigma delta -modulaattori satelliittipaikannusjĂ€rjestelmien (GNSS) vastaanottimeen. Arkkitehtuuriltaan modulaattori on kolmannen asteen 1-bittinen CTƩ∆M, jolla on 15MHz:n signaalikaistanleveys. YlinĂ€ytteistyssuhde on 25 ja AD muuntimen nĂ€ytteistystaajuus 768 MHz. Tavoitteena on saavuttaa teoreettinen 55 dB signaalikohinasuhde (SNR). TĂ€mĂ€ työ keskittyy jatkuva-aikaisen sigma delta -modulaattorin suunnitteluun ja toteutukseen, perustuen diskreettiaikaisen Ʃ∆-modulaattorin periaatteisiin ja systeemitason simulointiin ja mallitukseen. Jatkuva-aikaisen sigma delta -modulaattorin kertoimien laskentamenetelmĂ€ esitetÀÀn yksityiskohtaisesti, ja vaatimusten tĂ€yttyminen varmistetaan “top-down” -suunnitteluperiaatteella. LiitteenĂ€ on kertoimien laskemiseen kĂ€ytetty MATLAB-koodi. Jatkuva-aikaisten sigma delta -modulaattoreiden erityishaasteiden, liian pitkĂ€n silmukkaviiveen ja kellojitterin herkkyyden, voittamiseksi tutkitaan kahta strategiaa, viiveen kompensointipolkua ja FIR takaisinkytkentĂ€ -DA muunninta. Viivekompensointipolkua kĂ€yttĂ€mĂ€llĂ€ modulaattorin stabiilisuus ja kohinansuodatusfunktio saadaan varmistettua ja korjattua. LisĂ€ksi FIR takaisinkytkentĂ€ -DA-muuntimen kĂ€yttö pienentÀÀ kellojitteriherkkyyttĂ€, parantaen jatkuva aikaisen sigma delta -modulaattorin kokonaissuorituskykyĂ€ ja luotettavuutta. Toteutetuissa jatkuva-aikaisissa sigma delta -modulaattoreissa on kytketty perĂ€kkĂ€in integraattoreita myötĂ€kytkentĂ€rakenteella (CIFF) ja toisessa sekĂ€ myötĂ€- ettĂ€ takaisinkytkentĂ€rakenteella (CIFF-B). PÀÀhuomio on CIFF-B rakenteessa, joka toteutetaan 22nm CMOS prosessissa kĂ€yttĂ€en 0.8 voltin kĂ€yttöjĂ€nnitettĂ€. Suorityskyky varmistetaan erilaisilla simuloinneilla, joiden perusteella 55 dB SNR saavutetaan 1.36 mW tehonkulutuksella. LisĂ€ksi kohinanmuokkausfunktion optimoinnilla SNR saadaan nostettua 62 desibeliin

    Contribution to the design of continuous -time Sigma - Delta Modulators based on time delay elements

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    The research carried out in this thesis is focused in the development of a new class of data converters for digital radio. There are two main architectures for communication receivers which perform a digital demodulation. One of them is based on analog demodulation to the base band and digitization of the I/Q components. Another option is to digitize the band pass signal at the output of the IF stage using a bandpass Sigma-Delta modulator. Bandpass Sigma- Delta modulators can be implemented with discrete-time circuits, using switched capacitors or continuous-time circuits. The main innovation introduced in this work is the use of passive transmission lines in the loop filter of a bandpass continuous-time Sigma-Delta modulator instead of the conventional solution with gm-C or LC resonators. As long as transmission lines are used as replacement of a LC resonator in RF technology, it seems compelling that transmission lines could improve bandpass continuous-time Sigma-Delta modulators. The analysis of a Sigma- Delta modulator using distributed resonators has led to a completely new family of Sigma- Delta modulators which possess properties inherited both from continuous-time and discretetime Sigma-Delta modulators. In this thesis we present the basic theory and the practical design trade-offs of this new family of Sigma-Delta modulators. Three demonstration chips have been implemented to validate the theoretical developments. The first two are a proof of concept of the application of transmission lines to build lowpass and bandpass modulators. The third chip summarizes all the contributions of the thesis. It consists of a transmission line Sigma-Delta modulator which combines subsampling techniques, a mismatch insensitive circuitry and a quadrature architecture to implement the IF to digital stage of a receiver

    A design tool for high-resolution high-frequency cascade continuous- time Σ∆ modulators

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    Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, SpainThis paper introduces a CAD methodology to assist the de signer in the implementation of continuous-time (CT) cas- cade Σ∆ modulators. The salient features of this methodology ar e: (a) flexible behavioral modeling for optimum accuracy- efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; a nd (c) mixed knowledge-based and optimization-based architec- tural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT Σ∆ modulator in a 1.2V 130nm CMOS technology.Ministerio de Ciencia y Educación TEC2004-01752/MICMinisterio de Industria, Turismo y Comercio FIT-330100-2006-134 SPIRIT Projec

    A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications

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    A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15 ”m FDSOI CMOS process. The overall power efficiency is attained by employing a single-bit ΔΣ and a subthreshold FDSOI process. The loop-filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110 ”W power from a 1.5 V power supply when clocked at 6.144 MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) for the third-order, single-bit CT-ΔΣ modulator is 0.271 pJ/level

    Contribución al modelado y diseño de moduladores sigma-delta en tiempo continuo de baja relación de sobremuestreo y bajo consumo de potencia

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    Continuous-Time Sigma-Delta modulators are often employed as analog-to-digital converters. These modulators are an attractive approach to implement high-speed converters in VLSI systems because they have low sensitivity to circuit imperfections compared to other solutions. This work is a contribution to the analysis, modelling and design of high-speed Continuous-Time Sigma-Delta modulators. The resolution and the stability of these modulators are limited by two main factors, excess-loop delay and sampling uncertainty. Both factors, among others, have been carefully analysed and modelled. A new design methodology is also proposed. It can be used to get an optimum high-speed Continuous-Time Sigma-Delta modulator in terms of dynamic range, stability and sensitivity to sampling uncertainty. Based on the proposed design methodology, a software tool that covers the main steps has been developed. The methodology has been proved by using the tool in designing a 30 Megabits-per-second Continuous-Time Sigma-Delta modulator with 11-bits of dynamic range. The modulator has been integrated in a 0.13-”m CMOS technology and it has a measured peak SNR of 62.5dB

    Timing Jitter Analysis and Mitigation in Hybrid OFDM-DFMA PONs

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    Hybrid orthogonal frequency division multiplexing-digital filter multiple access passive optical networks (OFDM-DFMA PONs) offer a cost-effective solution to the challenging requirements of next-generation optical access networks and 5G and beyond radio access networks. It is crucial to consider the impact of timing jitter in any ADC/DAC-based system, therefore this paper presents an in-depth investigation into the impacts of DAC/ADC timing jitter on the hybrid OFDM-DFMA PON's performance. We introduce improved accuracy white and coloured, DAC and ADC timing jitter models, applicable to any DSP-based transmission system. We prove that DAC and ADC timing jitter effects are virtually identical and investigate the effects of white/coloured timing jitter on upstream performance in hybrid OFDM-DFMA PONs and determine the associated jitter-induced optical power penalties. To mitigate against the timing jitter-induced performance degradations, a simple, but highly effective DSP-based technique is implemented which increases robustness against the timing jitter effects and significantly reduces timing jitter-induced optical power penalties. This consequently relaxes DAC/ADC sampling clock jitter requirements and so reduces implementation costs. White (coloured) timing jitter effects are shown to be independent of (dependent on) ONU operating frequency band and a trade-off between DAC and ADC jitter levels can be exploited to reduce ONU costs
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