1,799 research outputs found

    NANOCONTROLLER PROGRAM OPTIMIZATION USING ITE DAGS

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    Kentucky Architecture nanocontrollers employ a bit-serial SIMD-parallel hardware design to execute MIMD control programs. A MIMD program is transformed into equivalent SIMD code by a process called Meta-State Conversion (MSC), which makes heavy use of enable masking to distinguish which code should be executed by each processing element. Both the bit-serial operations and the enable masking imposed on them are expressed in terms of if-then-else (ITE) operations implemented by a 1-of-2 multiplexor, greatly simplifying the hardware. However, it takes a lot of ITEs to implement even a small program fragment. Traditionally, bit-serial SIMD machines had been programmed by expanding a fixed bitserial pattern for each word-level operation. Instead, nanocontrollers can make use of the fact that ITEs are equivalent to the operations in Binary Decision Diagrams (BDDs), and can apply BDD analysis to optimize the ITEs. This thesis proposes and experimentally evaluates a number of techniques for minimizing the complexity of the BDDs, primarily by manipulating normalization ordering constraints. The best method found is a new approach in which a simple set of optimization transformations is followed by normalization using an ordering determined by a Genetic Algorithm (GA)

    A satisfiability procedure for quantified Boolean formulae

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    We present a satisfiability tester QSAT for quantified Boolean formulae and a restriction of QSAT to unquantified conjunctive normal form formulae. QSAT makes use of procedures which replace subformulae of a formula by equivalent formulae. By a sequence of such replacements, the original formula can be simplified to or . It may also be necessary to transform the original formula to generate a subformula to replace. eliminates collections of variables from an unquantified clause form formula until all variables have been eliminated. QSAT and can be applied to hardware verification and symbolic model checking. Results of an implementation of are described, as well as some complexity results for QSAT and . QSAT runs in linear time on a class of quantified Boolean formulae related to symbolic model checking. We present the class of “long and thin” unquantified formulae and give evidence that this class is common in applications. We also give theoretical and empirical evidence that is often faster than Davis and Putnam-type satisfiability checkers and ordered binary decision diagrams (OBDDs) on this class of formulae. We give an example where is exponentially faster than BDDs

    Shuttle/TDRSS Ku-band downlink study

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    Assessing the adequacy of the baseline signal design approach, developing performance specifications for the return link hardware, and performing detailed design and parameter optimization tasks was accomplished by completing five specific study tasks. The results of these tasks show that the basic signal structure design is sound and that the goals can be met. Constraints placed on return link hardware by this structure allow reasonable specifications to be written so that no extreme technical risk areas in equipment design are foreseen. A third channel can be added to the PM mode without seriously degrading the other services. The feasibility of using only a PM mode was shown to exist, however, this will require use of some digital TV transmission techniques. Each task and its results are summarized

    Study of a navigation and traffic control technique employing satellites. Volume 3 - User hardware Interim report

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    User hardware configurations and requirements for navigation and air traffic control technique using satellite

    A digital controller using multirate sampling for gain control

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    Digital controller using multirate sampling for gain contro

    Engineering evaluations and studies. Volume 3: Exhibit C

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    High rate multiplexes asymmetry and jitter, data-dependent amplitude variations, and transition density are discussed

    Control of sectioned on-chip communication

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    Cal Poly Supermileage Dynamometer

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    Our senior project involves designing a chassis dynamometer capable of simulating variable loads for the Cal Poly Supermileage Vehicle (SMV) team. The chassis dynamometer we are developing uses an alternator to develop additional resistance that the vehicle will have to overcome while testing. To implement a control system for the variable load, we use an Arduino Nano paired with multiple sensors and drivers. This control system allows the user to select different levels of resistance that correlate with different road grades. We designed a custom Printed Circuit Board (PCB) that will contain all the electrical components needed for the control system. We designed a mechanical system that makes use of belt drive pulleys to link the resistance provided by the alternator to the rotating drum and shaft assembly. Our final design also includes a software system with a Graphical User Interface (GUI) that allows for users of the SMV team to easily select various road grades and see the results of their dynamometer testing. Our design will allow the SMV team to make more efficient upgrades to the powertrain of both their gas and electric vehicles

    Address generator synthesis

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