Parameterized modeling of multiport passive circuit blocks

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 97-99).System level design optimization has recently started drawing the attention of circuit designers. A system level optimizer would search over the entire design space, adjusting the parameters of interest, for optimal performance metrics. These optimizers demand for the availability of parameterized compact dynamical models of all individual modules. The parameters may include geometrical parameters, such as width and spacing for an inductor or design parameters such as center frequency or characteristic impedance in case of distributed transmission line structures. The parameterized models of individual blocks need to be compact and passive since the optimizer would be solving differential equations (time domain integration or periodic steady state methods) to compute the performance metrics. Additionally, these parameterized models would be able to facilitate the job of the designer who could instantiate the models with different parameter value during manual optimization. In this thesis, we have designed and implemented various highly efficient algorithms for the identification of individual and parameterized models for multiport passive structures. The algorithms are based on convex relaxations of the original non-convex problem consisting of modeling multiport devices from frequency response data. Passivity is enforced in the final models by constrained fitting, where the constraints are either Linear Matrix Inequalities or semidefinite constraints. These individual non-parameterized models can be used for system level simulations for fixed parameter values or for building up a parameterized model. In the first algorithm, we identify a collection of first and second order networks to model individual non-parameterized passive blocks. Passivity of the overall model is guaranteed by enforcing passivity on the individual building blocks. In the second algorithm we exploit the property of causal and stable systems for which the real and imaginary parts of the frequency response are related by the Hilbert transform, by minimizing only the mismatch between real parts. Passivity is enforced in the identified model using semidefinte constraints. In this thesis we also propose an algorithm for generating parameterized multiport models of linear systems that the user will be able to instantiate for any parameter value, always obtaining a stable and passive model. Our approach uses constrained optimization to construct a parameterized model that optimally fits a set of given non-parameterized models using polynomial or rational basis. By using optimization, as opposed to interpolation as in the available parameterized modeling techniques, we are capable of guaranteeing global passivity with respect to the parameters, while simultaneously keeping the number of terms describing the model small. The proposed algorithms are supported by various modeling examples including Wilkinson combiners, power and ground distribution grid, on-chip coupled inductors, microstrip patch antenna and parameterized attenuator. The identified models are verified for passivity using the Hamiltonian matrix based eigenvalue test. Several comparisons with existing techniques are also provided, which demonstrate a promising speed up of 40x in some cases and an amazing efficiency, by generating a highly accurate model in the cases where alternative techniques even failed to generate the model.by Zohaib Mahmood.S.M

Modeling and Optimization of the Microwave PCB Interconnects Using Macromodel Techniques

L'abstract è presente nell'allegato / the abstract is in the attachmen

Switched-capacitor networks for image processing : analysis, synthesis, response bounding, and implementation

Thesis (Sc. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 279-284).by Mark N. Seidel.Sc.D

SPATIAL TRANSFORMATION PATTERN DUE TO COMMERCIAL ACTIVITY IN KAMPONG HOUSE

ABSTRACT Kampung houses are houses in kampung area of the city. Kampung House oftenly transformed into others use as urban dynamics. One of the transfomation is related to the commercial activities addition by the house owner. It make house with full private space become into mixused house with more public spaces or completely changed into full public commercial building. This study investigate the spatial transformation pattern of the kampung houses due to their commercial activities addition. Site observations, interviews and questionnaires were performed to study the spatial transformation. This study found that in kampung houses, the spatial transformation pattern was depend on type of commercial activities and owner perceptions, and there are several steps of the spatial transformation related the commercial activity addition. Keywords: spatial transformation pattern; commercial activity; owner perception, kampung house; adaptabilit

Circuit synthesizable guaranteed passive modeling for multiport structures

In this paper we present a highly efficient algorithm to automatically generate circuit synthesizable dynamical models for passive multiport structures. The algorithm is based on a natural convex relaxation of the original nonconvex problem of modeling multiport devices from frequency response data, subject to global passivity constraints. The algorithm identifies a collection of first and second order passive networks interconnected in either series or parallel fashion. Passive models for several multiport structures, including Wilkinson type combiners, power and ground distribution grids and coupled on-chip inductors are provided to corroborate the theoretical development and show efficacy of the implemented algorithm. To demonstrate the practical usage of our algorithm, the identified models are also interfaced with commercial simulators and used to perform time domain simulations while being connected to highly nonlinear power amplifiers.United States. Defense Advanced Research Projects AgencySemiconductor Research Corporation. Center for Circuits and Systems SolutionsFocus Center Research Program. Focus Center for Circuit & System Solutions. Semiconductor Research Corporation. Interconnect Focus Cente

Towards an embedded board-level tester: study of a configurable test processor

The demand for electronic systems with more features, higher performance, and less power consumption increases continuously. This is a real challenge for design and test engineers because they have to deal with electronic systems with ever-increasing complexity maintaining production and test costs low and meeting critical time to market deadlines. For a test engineer working at the board-level, this means that manufacturing defects must be detected as soon as possible and at a low cost. However, the use of classical test techniques for testing modern printed circuit boards is not sufficient, and in the worst case these techniques cannot be used at all. This is mainly due to modern packaging technologies, a high device density, and high operation frequencies of modern printed circuit boards. This leads to very long test times, low fault coverage, and high test costs. This dissertation addresses these issues and proposes an FPGA-based test approach for printed circuit boards. The concept is based on a configurable test processor that is temporarily implemented in the on-board FPGA and provides the corresponding mechanisms to communicate to external test equipment and co-processors implemented in the FPGA. This embedded test approach provides the flexibility to implement test functions either in the external test equipment or in the FPGA. In this manner, tests are executed at-speed increasing the fault coverage, test times are reduced, and the test system can be adapted automatically to the properties of the FPGA and devices located on the board. An essential part of the FPGA-based test approach deals with the development of a test processor. In this dissertation the required properties of the processor are discussed, and it is shown that the adaptation to the specific test scenario plays a very important role for the optimization. For this purpose, the test processor is equipped with configuration parameters at the instruction set architecture and microarchitecture level. Additionally, an automatic generation process for the test system and for the computation of some of the processor’s configuration parameters is proposed. The automatic generation process uses as input a model known as the device under test model (DUT-M). In order to evaluate the entire FPGA-based test approach and the viability of a processor for testing printed circuit boards, the developed test system is used to test interconnections to two different devices: a static random memory (SRAM) and a liquid crystal display (LCD). Experiments were conducted in order to determine the resource utilization of the processor and FPGA-based test system and to measure test time when different test functions are implemented in the external test equipment or the FPGA. It has been shown that the introduced approach is suitable to test printed circuit boards and that the test processor represents a realistic alternative for testing at board-level.Der Bedarf an elektronischen Systemen mit zusätzlichen Merkmalen, höherer Leistung und geringerem Energieverbrauch nimmt ständig zu. Dies stellt eine erhebliche Herausforderung für Entwicklungs- und Testingenieure dar, weil sie sich mit elektronischen Systemen mit einer steigenden Komplexität zu befassen haben. Außerdem müssen die Herstellungs- und Testkosten gering bleiben und die Produkteinführungsfristen so kurz wie möglich gehalten werden. Daraus folgt, dass ein Testingenieur, der auf Leiterplatten-Ebene arbeitet, die Herstellungsfehler so früh wie möglich entdecken und dabei möglichst niedrige Kosten verursachen soll. Allerdings sind die klassischen Testmethoden nicht in der Lage, die Anforderungen von modernen Leiterplatten zu erfüllen und im schlimmsten Fall können diese Testmethoden überhaupt nicht verwendet werden. Dies liegt vor allem an modernen Gehäuse-Technologien, der hohen Bauteildichte und den hohen Arbeitsfrequenzen von modernen Leiterplatten. Das führt zu sehr langen Testzeiten, geringer Testabdeckung und hohen Testkosten. Die Dissertation greift diese Problematik auf und liefert einen FPGA-basierten Testansatz für Leiterplatten. Das Konzept beruht auf einem konfigurierbaren Testprozessor, welcher im On-Board-FPGA temporär implementiert wird und die entsprechenden Mechanismen für die Kommunikation mit der externen Testeinrichtung und Co-Prozessoren im FPGA bereitstellt. Dadurch ist es möglich Testfunktionen flexibel entweder auf der externen Testeinrichtung oder auf dem FPGA zu implementieren. Auf diese Weise werden Tests at-speed ausgeführt, um die Testabdeckung zu erhöhen. Außerdem wird die Testzeit verkürzt und das Testsystem automatisch an die Eigenschaften des FPGAs und anderer Bauteile auf der Leiterplatte angepasst. Ein wesentlicher Teil des FPGA-basierten Testansatzes umfasst die Entwicklung eines Testprozessors. In dieser Dissertation wird über die benötigten Eigenschaften des Prozessors diskutiert und es wird gezeigt, dass die Anpassung des Prozessors an den spezifischen Testfall von großer Bedeutung für die Optimierung ist. Zu diesem Zweck wird der Prozessor mit Konfigurationsparametern auf der Befehlssatzarchitektur-Ebene und Mikroarchitektur-Ebene ausgerüstet. Außerdem wird ein automatischer Generierungsprozess für die Realisierung des Testsystems und für die Berechnung einer Untergruppe von Konfigurationsparametern des Prozessors vorgestellt. Der automatische Generierungsprozess benutzt als Eingangsinformation ein Modell des Prüflings (device under test model, DUT-M). Das entwickelte Testsystem wurde zum Testen von Leiterplatten für Verbindungen zwischen dem FPGA und zwei Bauteilen verwendet, um den FPGA-basierten Testansatz und die Durchführbarkeit des Testprozessors für das Testen auf Leiterplatte-Ebene zu evaluieren. Die zwei Bauteile sind ein Speicher mit direktem Zugriff (static random-access memory, SRAM) und eine Flüssigkristallanzeige (liquid crystal display, LCD). Die Experimente wurden durchgeführt, um den Ressourcenverbrauch des Prozessors und Testsystems festzustellen und um die Testzeit zu messen. Dies geschah durch die Implementierung von unterschiedlichen Testfunktionen auf der externen Testeinrichtung und dem FPGA. Dadurch konnte gezeigt werden, dass der FPGA-basierte Ansatz für das Testen von Leiterplatten geeignet ist und dass der Testprozessor eine realistische Alternative für das Testen auf Leiterplatten-Ebene ist

Embedded electronic systems driven by run-time reconfigurable hardware

Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria

Intrinsic Hardware Evolution on the Transistor Level

This thesis presents a novel approach to the automated synthesis of analog circuits. Evolutionary algorithms are used in conjunction with a fitness evaluation on a dedicated ASIC that serves as the analog substrate for the newly bred candidate solutions. The advantage of evaluating the candidate circuits directly in hardware is twofold. First, it may speed up the evolutionary algorithms, because hardware tests can usually be performed faster than simulations. Second, the evolved circuits are guaranteed to work on a real piece of silicon. The proposed approach is realized as a hardware evolution system consisting of an IBM compatible general purpose computer that hosts the evolutionary algorithm, an FPGA-based mixed signal test board, and the analog substrate. The latter one is designed as a Field Programmable Transistor Array (FPTA) whose programmable transistor cells can be almost freely connected. The transistor cells can be configured to adopt one out of 75 different channel geometries. The chip was produced in a 0.6µm CMOS process and provides ample means for the input and output of analog signals. The configuration is stored in SRAM cells embedded in the programmable transistor cells. The hardware evolution system is used for numerous evolution experiments targeted at a wide variety of different circuit functionalities. These comprise logic gates, Gaussian function circuits, D/A converters, low- and highpass filters, tone discriminators, and comparators. The experimental results are thoroughly analyzed and discussed with respect to related work

Nouvelles approches pour la conception d'outils CAO pour le domaine des systèmes embarqués

Thèse numérisée par la Division de la gestion de documents et des archives de l'Université de Montréal