Investigations on electromagnetic noises and interactions in electronic architectures : a tutorial case on a mobile system

Electromagnetic interactions become critic in embedded and smart electronic structures. The increase of electronic performances confined in a finite volume or support for mobile applications defines new electromagnetic environment and compatibility configurations (EMC). With canonical demonstrators developed for tutorials and EMC experiences, this paper present basic principles and experimental techniques to investigate and control these severe interferences. Some issues are reviewed to present actual and future scientific challenges for EMC at electronic circuit level

Area Efficient Device Optimization for ESD Protection in High Speed Interface ICs

Electrostatic discharge (ESD) protection is considered as a vital step in integrated circuit (IC) manufacturing process. IC chips are unable to overcome the effects of transient events without adequate discharge protection. Recent trend in the industry has seen the incorporation of system level ESD protection within the IC chip. Incorporating system level on-chip ESD protection often increases cost, degrades circuit performance and consumes layout area which could otherwise be used for improving the circuit performance. These design challenges could be easily overcome if the parasitic components in a circuit were used for ESD protection. Despite the various design challenges, on-chip ESD protection is still desirable as it saves the area on the circuit board by eliminating the traditional ESD protection devices resulting in more compact circuits. Furthermore, using parasitic components while designing on-chip system level ESD protection can save layout area. In order to effectively implement this solution, a study on ESD events, protection circuits and high-speed ICs was carried out. Different types of ESD events and the different models pertaining to ESD events were studied and are discussed in detail. An overview of high-speed integrated circuits was also carried out with emphasis on the protection topologies that are commonly used. The ESD characteristics of parasitic PNP devices in rail-based ESD protection structure was then studied to summarize its viability as a protection circuit. The turn-on or breakdown voltage of the parasitic PNP is studied by technology computer aided design (TCAD) simulations performed in Silvaco software. The breakdown voltage, holding voltage, on resistance and failure current were studied and modeled to maximize ESD protection

Electromagnetic Compatibility Considerations for International Space Station Payload Developers

The International Space Station (ISS) is a laboratory for scientific research, innovative technology development, and global education. The ISS provides a number of facilities and platforms for payload developers and investigators to conduct biological, microgravity, and Earth and space observation science, as well as for performing technology development. Due to the unique nature of the ISS vehicle and its electrical power and data systems, achieving electromagnetic compatibility (EMC) with the vehicle requires special considerations by the payload developer. The ISS electromagnetic interference (EMI) requirements and test methods are based on MIL-STD-461, Electromagnetic Emissions and Susceptibility Requirements for the Control of Electromagnetic Interference, Revision C, and MIL-STD-462, Electromagnetic Interference Characteristics, Measurement of, respectively. The low source impedance of the test setup requires special considerations when designing or selecting EMI power filters and switched mode power supplies. Many filters, suited for later revisions of MIL-STD-461, will result in non-compliant designs. ISS electrical power system power quality requirements, imposed to protect the stability of the system, can also affect EMI filter design. The selection and use of commercial-off-the-shelf (COTS) equipment for ISS applications requires special considerations to meet both EMC and crew safety requirements. Furthermore, the ISS environment can provide unique immunity challenges; if the payload developer ignores these challenges, the result is a possible loss of science or impact to technology demonstration. The ISS provides a unique opportunity for the science and technology development community. However, in order to be successful, the payload developer must incorporate special EMC considerations, many of which will be presented

White paper on the future of plasma science and technology in plastics and textiles

This is the peer reviewed version of the following article: “Uros, C., Walsh, J., Cernák, M., Labay, C., Canal, J.M., Canal, C. (2019) White paper on the future of plasma science and technology in plastics and textiles. Plasma processes and polymers, 16 1 which has been published in final form at [doi: 10.1002/ppap.201700228]. This article may be used for non-commercial purposes in accordance with Wiley Terms and Conditions for Self-Archiving."This white paper considers the future of plasma science and technology related to the manufacturing and modifications of plastics and textiles, summarizing existing efforts and the current state‐of‐art for major topics related to plasma processing techniques. It draws on the frontier of plasma technologies in order to see beyond and identify the grand challenges which we face in the following 5–10 years. To progress and move the frontier forward, the paper highlights the major enabling technologies and topics related to the design of surfaces, coatings and materials with non‐equilibrium plasmas. The aim is to progress the field of plastics and textile production using advanced plasma processing as the key enabling technology which is environmentally friendly, cost efficient, and offers high‐speed processingPeer ReviewedPostprint (author's final draft

Electrochemical batteries for smart grid applications

This paper presents a comprehensive review of current trends in battery energy storage systems, focusing on electrochemical storage technologies for Smart Grid applications. Some of the batteries that are in focus for improvement include Lithium-ion, metal-air, Sodium-based batteries and flow batteries. A descriptive review of these batteries and their sub-types are explained along with their suitable applications. An overview of different types and classification of storage systems has been presented in this paper. It also presents an extensive review on different electrochemical batteries, such as lead-acid battery, lithium-based, nickel-based batteries and sodium-based and flow batteries for the purpose of using in electric vehicles in future trends. This paper is going to explore each of the available storage techniques out there based on various characteristics including cost, impact, maintenance, advantages, disadvantages, and protection and potentially make a recommendation regarding an optimal storage technique

Design considerations for space flight hardware

The environmental and design constraints are reviewed along with some insight into the established design and quality assurance practices that apply to low earth orbit (LEO) space flight hardware. It is intended as an introduction for people unfamiliar with space flight considerations. Some basic data and a bibliography are included

Investigating the Feasibility of Utilizing Carbon Nanotube Fibers for Spacesuit Dust Mitigation

Historical data from the Apollo missions has compelled NASA to identify dust mitigation of spacesuits and other components as a critical path prior to sending humans on potential future lunar exploration missions. Several studies thus far have proposed passive and active countermeasures to address this challenge. However, these technologies have been primarily developed and proven for rigid surfaces such as solar cells and thermal radiators. Integration of these technologies for spacesuit dust mitigation has remained an open challenge due to the complexity of suit design. Current research investigates novel methods to enhance integration of the Electrodynamic Dust Shield (EDS) concept for spacesuits. We leverage previously proven EDS concept developed by NASA for rigid surfaces and apply new techniques to integrate the technology into spacesuits to mitigate dust contamination. The study specifically examines the feasibility of utilizing Carbon Nanotube (CNT) yarns manufactured by Rice University as electrodes in spacesuit material. Proof of concept testing was conducted at NASA Kennedy Space Center using lunar regolith simulant to understand the feasibility of the proposed techniques for spacesuit application. Results from the experiments are detailed in this paper. Potential challenges of applying this technology for spacesuits are also identified

Transient Safe Operating Area (tsoa) For Esd Applications

A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD). A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins. The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs. The methodology for output pins includes defining ESD design targets under Human Metal Model (HMM) type stress in high voltage Laterally Diffused MOS (LDMOS) outputs. First, the assessment of standalone LDMOS robustness is performed, followed by establishment of protection design guidelines. Secondly, standalone clamp HMM robustness is evaluated and a prediction methodology for HMM type stress is developed based on standardized testing. Finally, LDMOS and protection clamp parallel protection conditions are identifie

Analysis of design strategies for RF ESD problems in CMOS circuits

This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip

Design, Characterization And Compact Modeling Of Novel Silicon Controlled Rectifier (scr)-based Devices For Electrostatic Discha

Electrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have been standardized as human body model (HBM), machine model (MM), charged device model (CDM) and international electrotechnical commission model (IEC) for control, monitor and test. In additional to the environmental control of ESD events during manufacturing, shipping and assembly, incorporating on-chip ESD protection circuits inside ICs is another effective solution to reduce the ESD-induced damage. This dissertation presents design, characterization, integration and compact modeling of novel silicon controlled rectifier (SCR)-based devices for on-chip ESD protection. The SCR-based device with a snapback characteristic has long been used to form a VSS-based protection scheme for on-chip ESD protection over a broad rang of technologies because of its low on-resistance, high failure current and the best area efficiency. The ESD design window of the snapback device is defined by the maximum power supply voltage as the low edge and the minimum internal circuitry breakdown voltage as the high edge. The downscaling of semiconductor technology keeps on squeezing the design window of on-chip ESD protection. For the submicron process and below, the turn-on voltage and sustain voltage of ESD protection cell should be lower than 10 V and higher than 5 V, respectively, to avoid core circuit damages and latch-up issue. This presents a big challenge to device/circuit engineers. Meanwhile, the high voltage technologies push the design window to another tough range whose sustain voltage, 45 V for instance, is hard for most snapback ESD devices to reach. Based on the in-depth elaborating on the principle of SCR-based devices, this dissertation first presents a novel unassisted, low trigger- and high holding-voltage SCR (uSCR) which can fit into the aforesaid ESD design window without involving any extra assistant circuitry to realize an area-efficient on-chip ESD protection for low voltage applications. The on-chip integration case is studied to verify the protection effectiveness of the design. Subsequently, this dissertation illustrate the development of a new high holding current SCR (HHC-SCR) device for high voltage ESD protection with increasing the sustain current, not the sustain voltage, of the SCR device to the latchup-immune level to avoid sacrificing the ESD protection robustness of the device. The ESD protection cells have been designed either by using technology computer aided design (TCAD) tools or through trial-and-error iterations, which is cost- or time-consuming or both. Also, the interaction of ESD protection cells and core circuits need to be identified and minimized at pre-silicon stage. It is highly desired to design and evaluate the ESD protection cell using simulation program with integrated circuit emphasis (SPICE)-like circuit simulation by employing compact models in circuit simulators. And the compact model also need to predict the response of ESD protection cells to very fast transient ESD events such as CDM event since it is a major ESD failure mode. The compact model for SCR-based device is not widely available. This dissertation develops a macromodeling approach to build a comprehensive SCR compact model for CDM ESD simulation of complete I/O circuit. This modeling approach offers simplicity, wide availability and compatibility with most commercial simulators by taking advantage of using the advanced BJT model, Vertical Bipolar Inter-Company (VBIC) model. SPICE Gummel-Poon (SGP) model has served the ICs industry well for over 20 years while it is not sufficiently accurate when using SGP model to build a compact model for ESD protection SCR. This dissertation seeks to compare the difference of SCR compact model built by using VBIC and conventional SGP in order to point out the important features of VBIC model for building an accurate and easy-CAD implement SCR model and explain why from device physics and model theory perspectives