Pipelined implementation of Jpeg image compression using Hdl

This thesis presents the architecture and design of a JPEG compressor for color images using VHDL. The system consists of major parts like color space converter, down sampler, 2-D DCT module, quantization, zigzag scanning and entropy coDing The color space conversion transforms the RGB colors to YCbCr color coDing The down sampling operation reduces the sampling rate of the color information (Cb and Cr). The 2-D DCT transform the pixel data from the spatial domain to the frequency domain. The quantization operation eliminates the high frequency components and the small amplitude coefficients of the co-sine expansion. Finally, the entropy coding uses run-length encoding (RLE), Huffman, variable length coding (VLC) and differential coding to decrease the number of bits used to represent the image. The JPEG compression is a lossy compression, since downsampling and quantization operations are irreversible. But the losses can be controlled in order to keep the necessary image quality; Architectures for these parts were designed and described in VHDL. The results were observed using Active-HDL simulator and the code being synthesized using xilinx ise for vertex-4 FPGA. This pipelined architecture has a minimum latency of 187 clock cycles

Reduced Cycle Spinning Method for the Undecimated Wavelet Transform

[EN] The Undecimated Wavelet Transform is commonly used for signal processing due to its advantages over other wavelet techniques, but it is limited for some applications because of its computational cost. One of the methods utilized for the implementation of the Undecimated Wavelet Transform is the one known as Cycle Spinning. This paper introduces an alternative Cycle Spinning implementation method that divides the computational cost by a factor close to 2. This work develops the mathematical background of the proposed method, shows the block diagrams for its implementation and validates the method by applying it to the denoising of ultrasonic signals. The evaluation of the denoising results shows that the new method produces similar denoising qualities than other Cycle Spinning implementations, with a reduced computational cost.This research was funded by grants number PGC2018-09415-B-I00 (MCIU/AEI/FEDER, UE) and TEC2015-71932-REDT.Rodríguez-Hernández, MA. (2019). Reduced Cycle Spinning Method for the Undecimated Wavelet Transform. Sensors. 19(12):1-16. https://doi.org/10.3390/s19122777S1161912Signal Processing Fourier and Wavelet Representationshttp://www.fourierandwavelets.org/SPFWR_a3.1_2012.pdfZhao, H., Zuo, S., Hou, M., Liu, W., Yu, L., Yang, X., & Deng, W. (2018). A Novel Adaptive Signal Processing Method Based on Enhanced Empirical Wavelet Transform Technology. Sensors, 18(10), 3323. doi:10.3390/s18103323Gradolewski, D., Magenes, G., Johansson, S., & Kulesza, W. (2019). A Wavelet Transform-Based Neural Network Denoising Algorithm for Mobile Phonocardiography. Sensors, 19(4), 957. doi:10.3390/s19040957Shikhsarmast, F., Lyu, T., Liang, X., Zhang, H., & Gulliver, T. (2018). Random-Noise Denoising and Clutter Elimination of Human Respiration Movements Based on an Improved Time Window Selection Algorithm Using Wavelet Transform. Sensors, 19(1), 95. doi:10.3390/s19010095Shensa, M. J. (1992). The discrete wavelet transform: wedding the a trous and Mallat algorithms. IEEE Transactions on Signal Processing, 40(10), 2464-2482. doi:10.1109/78.157290Li, M., & Ghosal, S. (2015). Fast Translation Invariant Multiscale Image Denoising. IEEE Transactions on Image Processing, 24(12), 4876-4887. doi:10.1109/tip.2015.2470601Hazarika, D., Nath, V. K., & Bhuyan, M. (2016). SAR Image Despeckling Based on a Mixture of Gaussian Distributions with Local Parameters and Multiscale Edge Detection in Lapped Transform Domain. Sensing and Imaging, 17(1). doi:10.1007/s11220-016-0141-8Sakhaee, E., & Entezari, A. (2017). Joint Inverse Problems for Signal Reconstruction via Dictionary Splitting. IEEE Signal Processing Letters, 24(8), 1203-1207. doi:10.1109/lsp.2017.2701815Ong, F., Uecker, M., Tariq, U., Hsiao, A., Alley, M. T., Vasanawala, S. S., & Lustig, M. (2014). Robust 4D flow denoising using divergence-free wavelet transform. Magnetic Resonance in Medicine, 73(2), 828-842. doi:10.1002/mrm.25176Rehman, N. ur, Abbas, S. Z., Asif, A., Javed, A., Naveed, K., & Mandic, D. P. (2017). Translation invariant multi-scale signal denoising based on goodness-of-fit tests. Signal Processing, 131, 220-234. doi:10.1016/j.sigpro.2016.08.019Mota, H. de O., Vasconcelos, F. H., & de Castro, C. L. (2016). A comparison of cycle spinning versus stationary wavelet transform for the extraction of features of partial discharge signals. IEEE Transactions on Dielectrics and Electrical Insulation, 23(2), 1106-1118. doi:10.1109/tdei.2015.005300Li, D., Wang, Y., Lin, J., Yu, S., & Ji, Y. (2016). Electromagnetic noise reduction in grounded electrical‐source airborne transient electromagnetic signal using a stationarywavelet‐based denoising algorithm. Near Surface Geophysics, 15(2), 163-173. doi:10.3997/1873-0604.2017003San Emeterio, J. L., & Rodriguez-Hernandez, M. A. (2014). Wavelet Cycle Spinning Denoising of NDE Ultrasonic Signals Using a Random Selection of Shifts. Journal of Nondestructive Evaluation, 34(1). doi:10.1007/s10921-014-0270-8Rodriguez-Hernandez, M. A., & Emeterio, J. L. S. (2015). Noise reduction using wavelet cycle spinning: analysis of useful periodicities in the z-transform domain. Signal, Image and Video Processing, 10(3), 519-526. doi:10.1007/s11760-015-0762-8Rodriguez-Hernandez, M. A. (2016). Shift selection influence in partial cycle spinning denoising of biomedical signals. Biomedical Signal Processing and Control, 26, 64-68. doi:10.1016/j.bspc.2015.12.002Beylkin, G., Coifman, R., & Rokhlin, V. (1991). Fast wavelet transforms and numerical algorithms I. Communications on Pure and Applied Mathematics, 44(2), 141-183. doi:10.1002/cpa.3160440202Beylkin, G. (1992). On the Representation of Operators in Bases of Compactly Supported Wavelets. SIAM Journal on Numerical Analysis, 29(6), 1716-1740. doi:10.1137/0729097Donoho, D. L., & Johnstone, I. M. (1994). Ideal spatial adaptation by wavelet shrinkage. Biometrika, 81(3), 425-455. doi:10.1093/biomet/81.3.425Donoho, D. L., & Johnstone, I. M. (1995). Adapting to Unknown Smoothness via Wavelet Shrinkage. Journal of the American Statistical Association, 90(432), 1200-1224. doi:10.1080/01621459.1995.10476626Johnstone, I. M., & Silverman, B. W. (1997). Wavelet Threshold Estimators for Data with Correlated Noise. Journal of the Royal Statistical Society: Series B (Statistical Methodology), 59(2), 319-351. doi:10.1111/1467-9868.00071Pardo, E., San Emeterio, J. L., Rodriguez, M. A., & Ramos, A. (2006). Noise reduction in ultrasonic NDT using undecimated wavelet transforms. Ultrasonics, 44, e1063-e1067. doi:10.1016/j.ultras.2006.05.101Donoho, D. L. (1995). De-noising by soft-thresholding. IEEE Transactions on Information Theory, 41(3), 613-627. doi:10.1109/18.382009Lázaro, J. C., San Emeterio, J. L., Ramos, A., & Fernández-Marrón, J. L. (2002). Influence of thresholding procedures in ultrasonic grain noise reduction using wavelets. Ultrasonics, 40(1-8), 263-267. doi:10.1016/s0041-624x(02)00149-xKarpur, P., Shankar, P. M., Rose, J. L., & Newhouse, V. L. (1987). Split spectrum processing: optimizing the processing parameters using minimization. Ultrasonics, 25(4), 204-208. doi:10.1016/0041-624x(87)90034-5Pardo, E., Emeterio, S. J. L., Rodriguez, M. A., & Ramos, A. (2008). Shift Invariant Wavelet Denoising of Ultrasonic Traces. Acta Acustica united with Acustica, 94(5), 685-693. doi:10.3813/aaa.91808

Discrete Wavelet Transforms

The discrete wavelet transform (DWT) algorithms have a firm position in processing of signals in several areas of research and industry. As DWT provides both octave-scale frequency and spatial timing of the analyzed signal, it is constantly used to solve and treat more and more advanced problems. The present book: Discrete Wavelet Transforms: Algorithms and Applications reviews the recent progress in discrete wavelet transform algorithms and applications. The book covers a wide range of methods (e.g. lifting, shift invariance, multi-scale analysis) for constructing DWTs. The book chapters are organized into four major parts. Part I describes the progress in hardware implementations of the DWT algorithms. Applications include multitone modulation for ADSL and equalization techniques, a scalable architecture for FPGA-implementation, lifting based algorithm for VLSI implementation, comparison between DWT and FFT based OFDM and modified SPIHT codec. Part II addresses image processing algorithms such as multiresolution approach for edge detection, low bit rate image compression, low complexity implementation of CQF wavelets and compression of multi-component images. Part III focuses watermaking DWT algorithms. Finally, Part IV describes shift invariant DWTs, DC lossless property, DWT based analysis and estimation of colored noise and an application of the wavelet Galerkin method. The chapters of the present book consist of both tutorial and highly advanced material. Therefore, the book is intended to be a reference text for graduate students and researchers to obtain state-of-the-art knowledge on specific applications

A 2D DWT architecture suitable for the Embedded Zerotree Wavelet Algorithm

Digital Imaging has had an enormous impact on industrial applications such as the Internet and video-phone systems. However, demand for industrial applications is growing enormously. In particular, internet application users are, growing at a near exponential rate. The sharp increase in applications using digital images has caused much emphasis on the fields of image coding, storage, processing and communications. New techniques are continuously developed with the main aim of increasing efficiency. Image coding is in particular a field of great commercial interest. A digital image requires a large amount of data to be created. This large amount of data causes many problems when storing, transmitting or processing the image. Reducing the amount of data that can be used to represent an image is the main objective of image coding. Since the main objective is to reduce the amount of data that represents an image, various techniques have been developed and are continuously developed to increase efficiency. The JPEG image coding standard has enjoyed widespread acceptance, and the industry continues to explore its various implementation issues. However, recent research indicates multiresolution based image coding is a far superior alternative. A recent development in the field of image coding is the use of Embedded Zerotree Wavelet (EZW) as the technique to achieve image compression. One of The aims of this theses is to explain how this technique is superior to other current coding standards. It will be seen that an essential part orthis method of image coding is the use of multi resolution analysis, a subband system whereby the subbands arc logarithmically spaced in frequency and represent an octave band decomposition. The block structure that implements this function is termed the two dimensional Discrete Wavelet Transform (2D-DWT). The 20 DWT is achieved by several architectures and these are analysed in order to choose the best suitable architecture for the EZW coder. Finally, this architecture is implemented and verified using the Synopsys Behavioural Compiler and recommendations are made based on experimental findings

Development of Lifting-based VLSI Architectures for Two-Dimensional Discrete Wavelet Transform

Two-dimensional discrete wavelet transform (2-D DWT) has evolved as an essential part of a modem compression system. It offers superior compression with good image quality and overcomes disadvantage of the discrete cosine transform, which suffers from blocks artifacts that reduces the quality of the inage. The amount of computations involve in 2-D DWT is enormous and cannot be processed by generalpurpose processors when real-time processing is required. Th·"efore, high speed and low power VLSI architecture that computes 2-D DWT effectively is needed. In this research, several VLSI architectures have been developed that meets real-time requirements for 2-D DWT applications. This research iaitially started off by implementing a software simulation program that decorrelates the original image and reconstructs the original image from the decorrelated image. Then, based on the information gained from implementing the simulation program, a new approach for designing lifting-based VLSI architectures for 2-D forward DWT is introduced. As a result, two high performance VLSI architectures that perform 2-D DWT for 5/3 and 9/7 filters are developed based on overlapped and nonoverlapped scan methods. Then, the intermediate architecture is developed, which aim a·: reducing the power consumption of the overlapped areas without using the expensive line buffer. In order to best meet real-time applications of 2-D DWT with demanding requirements in terms of speed and throughput parallelism is explored. The single pipelined intermediate and overlapped architectures are extended to 2-, 3-, and 4-parallel architectures to achieve speed factors of 2, 3, and 4, respectively. To further demonstrate the effectiveness of the approach single and para.llel VLSI architectures for 2-D inverse discrete wavelet transform (2-D IDWT) are developed. Furthermore, 2-D DWT memory architectures, which have been overlooked in the literature, are also developed. Finally, to show the architectural models developed for 2-D DWT are simple to control, the control algorithms for 4-parallel architecture based on the first scan method is developed. To validate architectures develcped in this work five architectures are implemented and simulated on Altera FPGA. In compliance with the terms of the Copyright Act 1987 and the IP Policy of the university, the copyright of this thesis has been reassigned by the author to the legal entity of the university, Institute of Technology PETRONAS Sdn bhd. Due acknowledgement shall always be made of the use of any material contained in, or derived from, this thesis

Hardware realization of discrete wavelet transform cauchy Reed Solomon minimal instruction set computer architecture for wireless visual sensor networks

Large amount of image data transmitting across the Wireless Visual Sensor Networks (WVSNs) increases the data transmission rate thus increases the power transmission. This would inevitably decreases the operating lifespan of the sensor nodes and affecting the overall operation of WVSNs. Limiting power consumption to prolong battery lifespan is one of the most important goals in WVSNs. To achieve this goal, this thesis presents a novel low complexity Discrete Wavelet Transform (DWT) Cauchy Reed Solomon (CRS) Minimal Instruction Set Computer (MISC) architecture that performs data compression and data encoding (encryption) in a single architecture. There are four different programme instructions were developed to programme the MISC processor, which are Subtract and Branch if Negative (SBN), Galois Field Multiplier (GF MULT), XOR and 11TO8 instructions. With the use of these programme instructions, the developed DWT CRS MISC were programmed to perform DWT image compression to reduce the image size and then encode the DWT coefficients with CRS code to ensure data security and reliability. Both compression and CRS encoding were performed by a single architecture rather than in two separate modules which require a lot of hardware resources (logic slices). By reducing the number of logic slices, the power consumption can be subsequently reduced. Results show that the proposed new DWT CRS MISC architecture implementation requires 142 Slices (Xilinx Virtex-II), 129 slices (Xilinx Spartan-3E), 144 Slices (Xilinx Spartan-3L) and 66 Slices (Xilinx Spartan-6). The developed DWT CRS MISC architecture has lower hardware complexity as compared to other existing systems, such as Crypto-Processor in Xilinx Spartan-6 (4828 Slices), Low-Density Parity-Check in Xilinx Virtex-II (870 slices) and ECBC in Xilinx Spartan-3E (1691 Slices). With the use of RC10 development board, the developed DWT CRS MISC architecture can be implemented onto the Xilinx Spartan-3L FPGA to simulate an actual visual sensor node. This is to verify the feasibility of developing a joint compression, encryption and error correction processing framework in WVSNs

Hardware realization of discrete wavelet transform cauchy Reed Solomon minimal instruction set computer architecture for wireless visual sensor networks

Large amount of image data transmitting across the Wireless Visual Sensor Networks (WVSNs) increases the data transmission rate thus increases the power transmission. This would inevitably decreases the operating lifespan of the sensor nodes and affecting the overall operation of WVSNs. Limiting power consumption to prolong battery lifespan is one of the most important goals in WVSNs. To achieve this goal, this thesis presents a novel low complexity Discrete Wavelet Transform (DWT) Cauchy Reed Solomon (CRS) Minimal Instruction Set Computer (MISC) architecture that performs data compression and data encoding (encryption) in a single architecture. There are four different programme instructions were developed to programme the MISC processor, which are Subtract and Branch if Negative (SBN), Galois Field Multiplier (GF MULT), XOR and 11TO8 instructions. With the use of these programme instructions, the developed DWT CRS MISC were programmed to perform DWT image compression to reduce the image size and then encode the DWT coefficients with CRS code to ensure data security and reliability. Both compression and CRS encoding were performed by a single architecture rather than in two separate modules which require a lot of hardware resources (logic slices). By reducing the number of logic slices, the power consumption can be subsequently reduced. Results show that the proposed new DWT CRS MISC architecture implementation requires 142 Slices (Xilinx Virtex-II), 129 slices (Xilinx Spartan-3E), 144 Slices (Xilinx Spartan-3L) and 66 Slices (Xilinx Spartan-6). The developed DWT CRS MISC architecture has lower hardware complexity as compared to other existing systems, such as Crypto-Processor in Xilinx Spartan-6 (4828 Slices), Low-Density Parity-Check in Xilinx Virtex-II (870 slices) and ECBC in Xilinx Spartan-3E (1691 Slices). With the use of RC10 development board, the developed DWT CRS MISC architecture can be implemented onto the Xilinx Spartan-3L FPGA to simulate an actual visual sensor node. This is to verify the feasibility of developing a joint compression, encryption and error correction processing framework in WVSNs