On the Behavioral Modeling of Integrated Circuit Output Buffers

The properties of common behavioral macromodels for single ended CMOS integrated circuits output buffers are discussed with the aim of providing criteria for an effective use of possible modeling options

Design of CMOS integrated circuits

Tato práce se zabývá problematikou návrhu a simulace analogových integrovaných obvodů v technologii CMOS. Hlavním zaměřením práce je navrhnoutí transkonduktančního zesilovače pracujícího s nízkým vstupním rozdílovým napětím. Ukázka dvoustupňového transkonduktačního zesilovače s kompenzačním RC prvkem. Vytvoření topografie zesilovače pomocí technologie AMIS 07.This work deals with issues of design and simulation of analog CMOS integrated circuit. The general aim is to design transconductance amplifier working with low input offset voltage. The two stage operational – transconductance amplifier with compensation RC element is presented. Creation topography amplifier by the help of technology AMIS 07.

Chaotic Oscillations in CMOS Integrated Circuits

Chaos is a purely mathematical term, describing a signal that is aperiodic and sensitive to initial conditions, but deterministic. Yet, engineers usually see it as an undesirable effect to be avoided in electronics. The first part of the dissertation deals with chaotic oscillation in complementary metal-oxide-semiconductor integrated circuits (CMOS ICs) as an effect behavior due to high power microwave or directed electromagnetic energy source. When the circuit is exposed to external electromagnetic sources, it has long been conjectured that spurious oscillation is generated in the circuits. In the first part of this work, we experimentally and numerically demonstrate that these spurious oscillations, or out-of-band oscillations are in fact chaotic oscillations. In the second part of the thesis, we exploit a CMOS chaotic oscillator in building a cryptographic source, a random number generator. We first demonstrate the presence of chaotic oscillation in standard CMOS circuits. At radio frequencies, ordinary digital circuits can show unexpected nonlinear responses. We evaluate a CMOS inverter coupled with electrostatic discharging (ESD) protection circuits, designed with 0.5 μm CMOS technology, for their chaotic oscillations. As the circuit is driven by a direct radio frequency injection, it exhibits a chaotic dynamics, when the input frequency is higher than the typical maximum operating frequency of the CMOS inverter. We observe an aperiodic signal, a broadband spectrum, and various bifurcations in the experimental results. We analytically discuss the nonlinear physical effects in the given circuit : ESD diode rectification, DC bias shift due to a non-quasi static regime operation of the ESD PN-junction diode, and a nonlinear resonant feedback current path. In order to predict these chaotic dynamics, we use a transistor-based model, and compare the model's performance with the experimental results. In order to verify the presence of chaotic oscillations mathematically, we build on an ordinary differential equation model with the circuit-related nonlinearities. We then calculate the largest Lyapunov exponents to verify the chaotic dynamics. The importance of this work lies in investigating chaotic dynamics of standard CMOS ICs that has long been conjectured. In doing so, we experimentally and numerically give evidences for the presence of chaotic oscillations. We then report on a random number generator design, in which randomness derives from a Boolean chaotic oscillator, designed and fabricated as an integrated circuit. The underlying physics of the chaotic dynamics in the Boolean chaotic oscillator is given by the Boolean delay equation. According to numerical analysis of the Boolean delay equation, a single node network generates chaotic oscillations when two delay inputs are incommensurate numbers and the transition time is fast. To test this hypothesis physically, a discrete Boolean chaotic oscillator is implemented. Using a CMOS 0.5 μm process, we design and fabricate a CMOS Boolean chaotic oscillator which consists of a core chaotic oscillator and a source follower buffer. Chaotic dynamics are verified using time and frequency domain analysis, and the largest Lyapunov exponents are calculated. The measured bit sequences do make a suitable randomness source, as determined via National Institute of Standards and Technology (NIST) standard statistical tests version 2.1

A notation for designing restoring logic circuitry in CMOS

We introduce a programming notation in which every syntactically correct program specifies a restoring logic component, i.e., a component whose outputs are permanently connected, via "not too many" transistors, to the power supply. It is shown how the specified components can be translated into transistor diagrams for CMOS integrated circuits. As these components are designed as strict hierarchies, it is hoped that the translation of the transistor diagrams into layouts for integrated circuits can be accomplished mechanically

CMOS INTEGRATED CIRCUITS FOR CAPACITIVE SENSORS INTERFACING

Since large scientific and economic interests reside in micro-electromechanical systems (MEMS), this thesis has been focused mainly on the design of read-out channels for capacitive integrated sensors. In the first Chapter an introduction on micro-electromechanical systems and their applications are presented. The mechanical structure of capacitive MEMS, their different transduction interfaces and their future applications in wireless sensor network are illustrated. In the second Chapter, an interface for a capacitive pressure sensor is described. First the details of the capacitance to voltage conversion interface are shown; then two different techniques used to correct the linearity error related to the sensor characteristic are explained. The first approach uses a non-linear analog amplifier, the second method uses an analog to digital converter with a non linear characteristic. In the third Chapter, an interface that converts capacitance variations produced by a capacitive pressure sensor in an output pulse width modulated (PWM) signal is shown. A detailed analysis of different contributions due to non-idealities sources of the circuit is discussed; a comparison between the theoretical prediction and experimental measurements on a test chip are shown. In the fourth Chapter, a second version of circuit presented in the third chapter is shown; the circuit have a reduced power consumption and a better immunity to disturbs. The working principle is described in details, a theoretical analysis underlines possible causes of non ideality identifying the strategies which allow to reduce the effect of these disturbances. In the fifth Chapter, the implementation of a sigma-delta analog to digital converter (SD-ADC) using the 45 nm CMOS process and with a sampling frequency of 1 GHz is presented. The design flow of two different SD-ADC is discussed; the two converters have respectively a feedback and a feedforward architecture. Finally in the sixth Chapter, a technique that allows to transform an operational transconductive amplifier (OTA) from class A to class-AB is presented. The advantages of the proposed method respect other techniques present in literature are shown, also some other improvements that is possible to get respect the original cell are discussed

Analysis of CMOS IC-based Hybrid Architecture for Edge Computing

With the rapid advancement of Internet of Things (IoT), mobile internet, and big data technologies, edge computing has emerged as a novel computing paradigm. In the hybrid architecture of edge computing,Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits play a pivotal role in empowering edge devices and servers with essential computing, storage, and communication capabilities. Despite their critical importance, CMOS integrated circuits in edge computing environments confront significant challenges in low-power electronics. These challenges include an increase in power density and a decrease in system stability and reliability. This paper delves into the key technologies of the hybrid architecture in edge computing and sheds light on the vital role of CMOS integrated circuits in edge devices. It introduces a novel approach for low-power electronics, which encompasses methods like optimization of double threshold voltage and refinement of algorithmic processes. These methods aim to tackle the power-efficiency issues while maintaining the performance of edge computing systems.Furthermore, the paper presents a detailed analysis of the proposed low-power techniques, focusing on how they can effectively reduce power consumption without compromising the functionality and efficiency of the edge computing systems. It concludes with a comprehensive discussion on the optimization results, highlighting the benefits and potential implications of implementing these low-power strategies in edge computing environments. This discussion not only underscores the importance of energy efficiency in edge computing but also opens new avenues for future research and development in this rapidly evolving field

Readout electronics for a High-Rate CSC detector

A readout system for a high-rate muon Cathode Strip Chamber (CSC) is described. The system, planned for use in the forward region of the ATLAS muon spectrometer, uses two custom CMOS integrated circuits to achieve good position resolution at a flux of up to 2,500 tracks/cm{sup 2}/s

A complementary MOS process

The complete sequence used to manufacture complementary metal oxide semiconductor (CMOS) integrated circuits is described. The fixed-gate array concept is presented as a means of obtaining CMOS integrated circuits in a fast and reliable fashion. Examples of CMOS circuits fabricated by both the conventional method and the fixed-gate array method are included. The electrical parameter specifications and characteristics are given along with typical values used to produce CMOS circuits. Temperature-bias stressing data illustrating the thermal stability of devices manufactured by this process are presented. Results of a preliminary study on the radiation sensitivity of circuits manufactured by this process are discussed. Some process modifications are given which have improved the radiation hardness of our CMOS devices. A formula description of the chemicals and gases along with the gas flow rates is also included