A readout system for a high-rate muon Cathode Strip Chamber (CSC) is described. The system, planned for use in the forward region of the ATLAS muon spectrometer, uses two custom CMOS integrated circuits to achieve good position resolution at a flux of up to 2,500 tracks/cm{sup 2}/s

Gratchev, V

Kandasamy, A

O'Connor, P

Parsons, J

Polychronakos, V

Sippach, W

Tcherniatine, V

CERN Document Server

READOUT ELECTRONICS FOR A HIGH-RATE CSC DETECTORP. O’Connor (poc@bnl.gov), V. Gratchev, A. Kandasamy, V. Polychronakos, V. Tcherniatine,BNL, Upton, NY, USAJ. Parsons, W. Sippach, Columbia University Nevis Laboratories, Irvington, NY, USAAbstractA readout system for a high-rate muon Cathode StripChamber (CSC) is described. The system, planned for usein the forward region of the ATLAS muon spectrometer,uses two custom CMOS integrated circuits to achievegood position resolution at a flux of up to 2500tracks/cm2/s.1.  THE ATLAS CSC SYSTEMThe CSC system forms the forward section of themuon spectrometer of ATLAS. It consists of 64 four-layer chambers of 768 x- and 96 y-strips. Interpolation isperformed on the x-strips to achieve a resolution of about50 Pm in the precision coordinate. Front end electronicscards are located around the perimeter of each chamberand enclosed by a Faraday shield. With 32 chambers perendcap the total channel count is 55,000. Fiber optic linkstransfer digital data, clock, and control signals to andfrom each chamber.The acceptance of the CSC system is from 2.1 < |K| <2.7, resulting in an expected flux as shown in Fig. 2 (ratesincorporate a standard “safety factor” of 5). Strips in thehigh-K region will experience an average rate of about600 kHz, taking into account the spread of charge on thecathode plane. Monte Carlo simulation shows that pileupeffects can be tolerated if a bipolar pulse shape with awidth less than about 1/5 of the average interpulse time isused.Signals from each strip are amplified, filtered, andsampled at 40 Msa/s. Sampled data are stored on-chamber for the duration of the Level 1 trigger latency.To minimize the cost and power of the on-detectorelectronics, a switched-capacitor array (SCA) performsthe sampling and storage in the analog domain. Uponreceipt of a valid Level 1 trigger, the appropriate samplesare read out, digitized, zero suppressed, and transmittedover fiber optic links to the read out drivers (RODs).At a trigger rate of 100 kHz, and assuming ten 10-bittime samples to be read out per channel, per trigger, thegross digitization rate for the CSC system is 6!104 chan.Z 105 Hz ! 10b ! 10 samples = 6!1011 bits/s.Since chamber occupancy is of order 10%, simple zerosuppression alone is not sufficient to reduce the datavolume to a manageable level. It will also be necessary tosuppress data belonging to out-of-time events, and  totrack segments which do not project back towards theinteraction point. Overall, a reduction of about 8Z -- 20Zis expected. The remaining data, about 1 Gbit/s perchamber, will be transmitted on optical fiber to the RODs,where space points will be extracted by interpolation.2.  SIGNAL PROCESSING2.1  Pulse ShapingBecause we require a high SNR at high data rates, thesignal processing is a tradeoff of rate-handling abilityversus noise.  By Monte Carlo analysis, it is found thatthe  pileup effects can be avoided if the width of the pulseat the 1% level (FW1%M) is less than 430 ns.Conventional pulse shaping filters, which use cascadedreal poles, produce an asymmetric quasi-Gaussian pulsewhich becomes more symmetric as the filter order isincreased. By using a pulse shaper with complex poles,more symmetric pulses can be obtained with a lower filterorder. Hence, we can obtain lower series noise for thesame filter order, or lower number of filter stages (thuslower power consumption) for the same noise. A bipolarpulse shape was selected, as its ability to reject lowfrequency noise, drift, and ion tails was deemed tocompensate for the small increase in series noise.2.2 Signal to NoiseIn an interpolating system the fractional positionresolution is related to signal to noise ratio (SNR) asVx/x = k VQ/Qwhere Vx/x is the position resolution as a fraction of theinterstrip spacing, Q/VQ is the signal to equivalent noisecharge ratio, and k is a constant of order 1. To achieve thedesired fractional resolution of 1% the SNR must be oforder 200. The ionization produced in these chambers bya normal incidence track is 90 ion pairs, leading to aninduced charge signal on the cathode strip of around 70fC. Hence to achieve the desired position resolution allsources of electronic noise must amount to less thanabout 2500 r.m.s. electrons.3. ELECTRONICS ORGANIZATIONEach chamber has eight 96-channel Amplifier-StorageModule (ASM) boards mounted around the chamberperiphery. These boards pick up the 768 x-strips from thefour precision cathode planes. The charge signals areamplified and filtered by preamp/shaper (P/S) ASICs (12channels per chip) and the amplified pulses are thensampled and stored in the SCA. The ASM board containseight P/S, SCA, and ADC chips, along with control logicin a 12 x 24 x 0.5 cm volume. The raw data from theASM at a rate of about 1 Gbit/s is sent to the dataconcentrator on LVDS links.A possible layout of the ASM board is shown in Figure1.Figure 2 shows a diagram of the ASM board mountingon the chambers.In Figure 3, the organization of the readout of oneendcap is shown.Figure 1Figure 2C ha m b er  B o u n da ryA SM  # 1A SM  # 1.....2 3 961A SM  # 22 3 961A SM  # 82 3 961D ata  C o nce n tra to r (X   1 /1 0 )T T CR C V RD C SR C V RVME Crate2 3 4 5 6 7 89 10 11 12 13 14 15 1625 26 27 28 29 30 31 3217 18 19 20 21 22 23 24DCS TTC RODs1 Gbit/s800 Mbit/sChamber #1Figure 34. PREAMP/SHAPER ASIC4.1 Preamp input transistor optimizationThe input device  is chosen to be an NMOStransistor with minimum channel length. Then, thewidth is selected to give minimum noise for theallotted power budget. Using the standard analysis thedevice width that minimizes series white noise is theone that gives a FET capacitance of CDet/3. However,with 0.5Pm CMOS and input capacitance of 50 pF  thedevice would be biased in the weak inversion regionwhere the standard analysis is no longer valid. Wereduce the device width to put it near the border ofweak-strong inversion to achieve a lower capacitanceat the same gm. Finally, a behavioral model inMathCAD is used to select the input devicedimensions. The current source and cascode devices inthe preamp are also chosen for low noise using thismode.   4.2 DC feedback and compensationFor our expected strip capacitance of 20 – 50 pF wechoose a preamplifier feedback capacitance of 1.2 pF.A NMOS FET biased in the triode region is used forDC feedback with an equivalent resistance of about 1.2M:, which gives negligible parallel noise and keepsthe reset time short enough to prevent the preamp fromsaturating under the highest expected rate. The bias isprovided by a replica circuit which sets the feedbackFET’s gate potential with reference to the input/outputpotential of the amplifier; it is essential to use such ascheme which tracks temperature and process variationto prevent excessive variation of the effective RF.The compensation circuit is a nonlinear version ofthe standard pole-zero compensation used in discretedesigns. The compensation FET sees the same gate,source, and drain voltage as the feedback FET and sothe two devices maintain a constant resistance ratioeven as the preamp output swings in response to alarge transient signal. In practice the feedback FETnonlinearity is well-compensated by this system.4.3 ShaperThe method of Ohkawa [1] is used to design a 7thorder shaper which is the best approximation to a trueGaussian waveform. The shaper has a single real poleand three second-order sections in cascade. Eachsecond-order section is made with a multiple feedbacktopology. This arrangement uses a high-gain invertingamplifier whose input serves as a virtual ground, andhas low sensitivity to component tolerances.The amplifier stages used in the shaper are NMOS-input folded cascodes with a gain-bandwidth productof about 200 MHz. The amplifiers dissipate about 3mW each. Small current sources at the inputs of eachamplifiers allow the input and output DC levels todiffer, where necessary to maintain high dynamicrange.The final stage is a symmetric OTA with rail-to-railclass AB output. Dissipating only 5 mW, this circuitcan drive up to 400 pF capacitive loads to within 0.1Vof either supply rail at slew rates of over 50 V/Psec.A block diagram of the P/S is shown in Figure 4.Figure 45. SCAThe SCA developed for the ATLAS Liquid Argoncalorimeter [2] is well-suited for use in the CSCsystem. It is organized as 4 groups of (3 + 1 reference)channels, and is capable of simultaneous read and writeat 40 MHz with 12 bit resolution. The readout logic ofthe LAr SCA is internally set to multiplex the outputsof two chips into a single ADC; a modification to theIC has been implemented to allow each SCA to be readout into its own ADC for higher throughput. Otherwisethe architecture and pinout of the chip is unchanged.6. P/S RESULTSThe first prototype of the CSC P/S was receivedfrom the foundry in early September 1999 and wasfound to function in very close agreement tosimulations. Figure 5 shows the simulated (solid line)and measured (dotted) waveforms.Noise and linearity results are shown in Figure 6 andFigure 7 respectively.To simulate the effect of high rates, double-pulsesignals at varying separations were injected. As shownin Figure 8, the interpulse spacing can be below 300nsec without any pileup.200 100 0 100 200 300 40010.500.51Time (ns)VoutFigure 50 20 40 60 80 100 120100015002000250030003500Cd (pF)ENC (rms e-)Figure 600.511.522.50 200 400 600Q in  (fC )Vout (V)Figure 7270 nsFigure 8470 pF100 :UNLOADEDFigure 9The Class AB output driver was able to drive lowimpedance loads with low distortion. Figure 9 showsthe output waveform of the P/S unloaded, and loadedby 470 pF and 100 .The performance of the P/S chip is summarized inTable I.Table ITechnology 0.5 Pm CMOSChannels 16Die size 2.78 x 3.96 mmArchitecture Single-endedIntended Cdet 20 – 100 pFInput device NMOS W/L = 5000/0.6 Pm,Id = 4mANoise 1140 + 17.6 e-/pFGain 3.8 mV/fCMax. linear charge 450 fCClass AB Output swing To power supply - 250 mVPulse shape 7th order complex Gaussian,bipolarPulse peaking time, 5% -100%73 nsFW1%M 340 nsMax. output loading (3%distortion)500 :, 500 pFCrosstalk 0.8% adjacent, 0.5% non-adjacent channelPower supply Single +3.3VPower Dissipation 32.5 mW/chan7. Conclusions and Future WorkThe front end electronics of the ATLAS CSC systemis in development. The custom ASICs, typically thelongest lead-time items in such a project, havecompleted one prototyping cycle and perform inaccordance with specifications. Future efforts in designwill concentrate on data selection/compessionalgorithms, controller hardware design, mechanics,interconnect, and cooling of the on-chambercomponents,  and design of the fiber links and RODs.The first performance test of a complete front endprototype chain will take place this year in a test beamwith high background simulation. Qualification testingfor radiation tolerance, both of the custom and COTscomponents, will begin in 2000.  Production is slatedfor 2001 - 2003.REFERENCES[1] Ohkawa, NIM 138 (1976) 85-92, "Direct Synthesesof the Gaussian Filter for Nuclear Pulse Amplifiers"[2] ATLAS Liquid Argon Calorimeter TechnicalDesign Report, Dec. 16, 1996

Readout electronics for a High-Rate CSC detector

O'Connor, P.

Gratchev, V.

Kandasamy, A.

Polychronakos, V.

Tcherniatine, V.

Parsons, J.

Sippach, W.

UNT (University of North Texas) Digital Library

Pmt. 5th Workshop on Ek-tmtticsJor LHC E~pen’me?ltsCERNY9-09, CERN/LHCC/99-33, pp. 452-456 (1999)BLVL-66642READOUT ELECTRONICS FOR .4 HIGH-RATE CSC DETECTOR”P. O’Connor, V. Gratchev, .~. Kandasamy, V. Polychronakos, and V. TcherniatineBrookhaven >-ational LaboratoryUpton, h-l” 11973-5000J. Pm-sons and W. SippachColumbia University N’evis LaboratoriesIrvington, ND?September, 1999‘Work supported in part by the U.S. Depxtrnent of Energ Contract No. DE-AC(12-98CH108 S6.READOUT ELECTRONICS FOR A HIGH-RATE CSC DETECTORP. O’Connor (poc(ij)bnl.gov), V. Gratchev, A. Kandasamy, V. Polychronakos, V. Tcherniatine,BNL, Upton, NY, USAJ. Parsons, W. Sippach, Columbia University Nevis Laboratories, Irvin.gton, NY, USAAbstractA readout system for a high-rate muon Cathode StripChamber (CSC) is described. The system, planned for usein the forward region of the ATLAS muon spectrometer,uses two custom CMOS integrated circuits to achievegood position resolution at a flux of up to 2500tracks/cm2/s.1. THE ATLAS CSC SYSTEMThe CSC system forms the forward section of themuon spectrometer of ATLAS. It consists of 64 four-layer chambers of 768 x- and 96 y-strips. Interpolation isperformed on the x-strips to achieve a resolution of about50 pm in the precision coordinate. Front end electronicscards are located around the perimeter of each chamberand enclosed by a Faraday shield. With 32 chambers perendcap the total channel count is 55,000. Fiber optic linkstransfer digital data, clock, and control signals to andfrom each chamber.The acceptance of the CSC system is from 2.1 < IqI <2.7, resulting in an expected flux as shown in Fig. 2 (ratesincorporate a standard “ safety factor” of 5). Strips in thehigh-q region will experience an average rate of about600 kHz, taking into account the spread of charge on thecathode plane. Monte Carlo simulation shows that pileupeffects can be tolerated if a bipolar pulse shape with awidth less than about 1/5 of the average interpulse time isused.Signals from each strip are amplified, filtered, andsampled at 40 Msa/s. Sampled data are stored on-chamber for the duration of the Level 1 trigger latency.To minimize the cost and power of the on-detectorelectronics, a switched-capacitor array (SCA) performsthe sampling and storage in the analog domain. Uponreceipt of a valid Level 1 trigger, the appropriate samplesare read out, digitized, zero suppressed, and transmittedover fiber optic links to the read out drivers (RODS).At a trigger rate of 100 kHz, and assuming ten 10-bittime samples to be read out per channel, per trigger, thegross digitization rate for the CSC system is 6=10q than. x105 Hz ● 10b ● 10 samples = 601011 bitsk.Since chamber occupancy is of order 10%, simple zerosuppression alone is not sufficient to reduce the datavolume to a manageable level. It will also be necessary tosuppress data belonging to out-of-time events, and totrack segments which do not project back towards theinteraction point. Overall, a reduction of about 8X -- 20xis expected. The remaining data, about 1 Gbit/s perchamber, will be transmitted on optical fiber to the RODS,where space points will be extracted by interpolation.2. SIGNAL PROCESSING2.1 Pulse ShapingBecause we require a high SNR at high data rates, thesignal processing is a tradeoff of rate-handling abilityversus noise. By Monte Carlo analysis, it is found thatthe pileup effects can be avoided if the width of the pulseat the 1°/0 level (FW1°/OM) is less than 430 ns.Conventional pulse shaping filters, which use cascadedreal poles, produce an asymmetric quasi-Gaussian pulsewhich becomes more symmetric as the filter order isincreased. By using a pulse shaper with complex poles,more symmetric pulses can be obtained with a lower filterorder. Hence, we can obtain lower series noise for thesame filter order, or lower number of filter stages (thuslower power consumption) for the same noise. A bipolarpulse shape was selected, as its ability to reject lowfrequency noise, drift, and ion tails was deemed tocompensate for the small increase in series noise.2.2 Signal to NoiseIn an interpolating system the fractional positionresolution is related to signal to noise ratio (SNR) asOx/x = k c@where a.Jx is the position resolution as a fraction of theinterstrip spacing, Q/0~ is the signal to equivalent noisecharge ratio, and k is a constant of order 1. To achieve thedesired fractional resolution of 1% the SNR must be oforder 200. The ionization produced in these chambers bya normal incidence track is 90 ion pairs, leading to aninduced charge signal on the cathode strip of around 70fC. Hence to achieve the desired position resolution allsources of electronic noise must amount to less thanabout 2500 r.m. s. electrons.3. ELECTRONICS ORGANIZATIONEach chamber has eight 96-channel Amplifier-StorageModule (ASM) boards mounted around the chamberperiphery. These boards pick up the 768 x-strips from thefour precision cathode planes. The charge signals are. -,=’.amplified and filtered by preamp/shaper (P/S) ASICS (12 ASM at a rate of about 1 Gbit/s is sent to the datachannels per chip) and the amplified pulses are then concentrator on LVDS links.sampled and stored in the SCA. The ASM board contains A possible layout of the ASM board is shown in Figureeight P/S, SCA, and ADC chips, along with control logic 1.in a 12 x 24 x 0.5 cm volume. The raw data from the4 - 240 >TransitionbardI~m ❑ O •1 •1 ~ ~A-luun~l l-----lmlxlmy)El El - lcoNTRouERI lcoNmoLLERI - El ElINPUTCONNECTOR 1:1 IF I IJJ~ INPUTCONNECTORw i-5iof the ASM board mountingFigure 2 shows a diagramon the chambers.~;-”’. ~-.. ..II ‘ /$Q“.>. %?’v:-.. ”,. *llgulc AIn Figure 3, the organization of the readout of oneendcap is shown.Ill I Ill Imm)-+-JIll I..... u.4%4mOcs TTC : oat. Co”cenbatm~~,”q %x? : ,“ 4,,.,,fi ,, ,”)I... . . . .~Chamber Boundary9 10 11 12 13 14 15 16I I I I I I I17 18 19 20 21 22 23 2425 26 27 28 29 30 31 32$4’$D(X lTC RODSvME Crate,.vFigure 3. -t.’4. PREAMP/SHAPER ASIC4.1 Preamp input transistor optimizationThe input device is chosen to be an NMOStransistor with minimum channel length. Then, thewidth is selected to give minimum noise for theallotted power budget. Using the standard analysis thedevice width that minimizes series white noise is theone that gives a FET capacitance of CDet/3. However,with 0.5pm CMOS and input capacitance of 50 pF thedevice would be biased in the weak inversion regionwhere the standard analysis is no longer valid. Wereduce the device width to put it near the border ofweak-strong inversion to achieve a lower capacitanceat the same gm. Finally, a behavioral model inMathCAD is used to select the input devicedimensions. The current source and cascode devices inthe preamp are also chosen for low noise using thismode.4.2 DC feedback and compensationFor our expected strip capacitance of 20 – 50 pF wechoose a preamplifier feedback capacitance of 1.Z pF.A NMOS FET biased in the triode region is used forDC feedback with an equivalent resistance of about 1.ZMf2, which gives negligible parallel noise and keepsthe reset time short enough to prevent the preamp fromsaturating under the highest expected rate. The bias isprovided by a replica circuit which sets the feedbackFET’s gate potential with reference to the input/outputpotential of the amplifier; it is essential to use such ascheme which tracks temperature and process variationto prevent excessive variation of the effective RF.The compensation circuit is a nonlinear version ofthe standard pole-zero compensation used in discretedesigns. The compensation FET sees the same gate,source, and drain voltage as the feedback FET and sothe two devices maintain a constant resistance ratioeven as the preamp output swings in response to alarge transient signal. In practice the feedback FETnonlinearity is well-compensated by this system.$.3 ShaperThe method of Ohkawa [l] is used to design a 7thorder shaper which is the best approximation to a trueGaussian waveform. The shaper has a single real poleand three second-order sections in cascade. Eachsecond-order section is made with a multiple feedbacktopology. This arrangement uses a high-gain invertingamplifier whose input serves as a virtual ground, andhas low sensitivity to component tolerances.The amplifier stages used in the shaper are NMOS-input folded cascodes with a gain-bandwidth productof about 200 MHz. The amplifiers dissipate about 3mW each. Small current sources at the inputs of eachamplifiers allow the input and output DC levels todiffer, where necessary to maintain high dynamicrange.The final stage is a symmetric OTA with rail-to-railclass AB output. Dissipating only 5 mW, this circuitcan drive up to 400 pF capacitive loads to within O.lVof either supply rail at slew rates of over 50 V/~sec.A block diagram of the P/S is shown in Figure 4.~4X Q28.8 31K11 1.45 pF1.2 pF II--P= 1>1 ‘:)- ‘N)- ‘)- “g’-Preamp Compensation1st Pole 2nd-order 2nd-order 2nd-order Class AB5.12 MHz Lowpass Lowpass Bandpasss Ouput Buffer5.24 MHz 5.63 MHz 6.51 ~tiz Gain = 2Q = .5234 Q = .6098 Q = .8549HO= 1.67 HO= 1.22 HO = 3.0Figure 4~-,.“●5. SCAThe SCA developed for the ATLAS Liquid Argoncalorimeter [2] is well-suited for use in the CSCsystem. It is organized as 4 groups of (3 + 1 reference)channels, and is capable of simultaneous read and writeat 40 MHz with 1Z bit resolution. The readout logic ofthe LAr SCA is internally set to multiplex the outputsof two chips into a single ADC; a modification to theIC has been implemented to allow each SCA to be readout into its own ADC for higher throughput. Otherwisethe architecture and pinout of the chip is unchanged.6. P/S RESULTSThe first prototype of the CSC P/S was receivedfrom the foundry in early September 1999 and wasfound to fimction in very close agreement tosimulations. Figure 5 shows the simulated (solid line)and measured (dotted) waveforms.1+.5-~200 -100 0 100 ~oo 300Time (ns)Figure 5:~o 20 40 60 80 I 00400!0Noise and linearity results are shown in Figure 6 andFigure 7 respectively.2.50 200 400 600Qin (fC)Figure 7L _mTmJ14_9mEm 20.Omv loons 0753,27Figure 8I[r[, ,, ,,, ] f,,, ,,,,\ : /’fThi ?urJnlv% 0.s Ln4 J ubu m~Figure 9To simulate the effect of high rates, double-pulsesignals at varying separations were injected. As shownin Figure 8, the interpulse spacing can be below 300nsec without any pileup.. .‘..’●The Class AB output driver was able to drive low REFERENCESimpedance loads with low distortion. Figure 9 showsthe output waveform of the P/S unloaded, and loaded[1] Ohkawa, NIM 138 (1976) 85-92, “Direct Synthesesby 470 pF and 100.of the Gaussian Filter for Nuclear Pulse Amplifiers”The performance of the P/S chip is summarized in[2] ATLAS Liquid Argon Calorimeter TechnicalTable I.Design Report, Dec. 16, 1996Table ITechnologyChannelsDie sizeArchitectureIntended CdetInput deviceNoiseGainMax. linear chargeClass AB Output swingPulse shapePu]se peaking time, j~o -1OovoFW1?40MMax. output loading (3V0distortion)CrosstalkPower supplyPower Dissipation0.5 pm CMOS162.78 x 3,96 mmSingle-ended20–100pFNMOS W/L = 5000/0.6 ~m,Id= 4mA1140 + 17.6 e-/pF3.8 mV/fC450 fcTo power supply -250 mV7’h order complex Gaussian.bipolar73 ns340 ns500 Q. 500 pF0.8V0 adjacent. ().s~. non-adjacent channelSingle +3.3V32.5 mW/than7. Conclusions and Future WorkThe front end electronics of the ATLAS CSC systemis in development. The custom ASICS, typically thelongest lead-time items in such a project, havecompleted one prototyping cycle and perform inaccordance with specifications. Future efforts in designwill concentrate on data selection/compassionalgorithms, controller hardware design, mechanics.interconnect, and cooling of the on-chambercomponents, and design of the fiber links and RODS.The first performance test of a complete front endprototype chain will take place this year in a test beamwith high background simulation. Qualification testingfor radiation tolerance, both of the custom and COTScomponents, will begin in 2000. Production is slatedfor 2001-2003.

Readout Electronics for a High-Rate CSC Detector

Readout electronics for a High-Rate CSC detector

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