A 14-mW PLL-less receiver in 0.18-μm CMOS for Chinese electronic toll collection standard

This is the accepted manuscript version of the following article: Xiaofeng He, et al., “A 14-mW PLL-less receiver in 0.18-μm CMOS for Chinese electronic toll collection standard”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61(10): 763-767, August 2014. The final published version is available at: http://ieeexplore.ieee.org/document/6871304/ © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The design of a 14-mW receiver without phase-locked loop for the Chinese electronic toll collection (ETC) system in a standard 0.18-μm CMOS process is presented in this brief. Since the previously published work was mainly based on vehicle-powered systems, low power consumption was not the primary goal of such a system. In contrast, the presented system is designed for a battery-powered system. Utilizing the presented receiver architecture, the entire receiver only consumes 7.8 mA, at the supply voltage of 1.8 V, which indicates a power saving of at least 38% compared with other state-of-the-art designs for the same application. To verify the performance, the bit error rate is measured to be better than 10-6, which well satisfies the Chinese ETC standard. Moreover, the sensitivity of the designed receiver can be readjusted to -50 dBm, which is required by the standard.Peer reviewe

A fully integrated RSSI and an ultra-low power SAR ADC for 5.8 GHz DSRC ETC transceiver

This study presents a monolithic received signal strength indicator (RSSI) and an ultra-low power SAR ADC for 5.8 GHz DSRC transceiver in China electronic toll collection systems. In order to meet the stringent requirement of wide input range for the transceiver, two RSSIs collaborate with auxiliary ADC circuits to provide the digitalized received signal strength to the digital baseband of a transceiver. The RSSI design achieves fast transient response and low power consumption with a small die area by using internal active low-pass filters instead of external passive ones. The proposed design has been fabricated using a 0.13 μm 2P6M CMOS technology. Measurement results show that the overall input dynamic range is 86 dB with an accuracy of ±1.72 dB and a transient response of less than 2 μs. Compared with the state-of-the-art designs in the literature, the overall input range and transient settling time are improved by at least 14.6%, and 300%, respectively

Design of a Limiting Amplifier for an Optical Receiver

The HEP experiments that take place at CERN’s LHC demand a multi-gigabit optical link for an efficient transmission of the resulting generated data. An optoelectronic link arises as the best solution given its possibility of working at high data rates and due to fiber’s imunnity to electromagnetic noise. The design of this optical link is particularly demanding due to the stringent data rate specifications (5Gb/s), the BER specification (1012) and the constraints imposed by radiation. In HEP, radiation is always a constraint so, the Optical Receiver circuit must be hardened in order to tolerate that kind of environment - radiation-tolerant. The core of a standard optoeletronic receiver includes a Photodiode, a Transimpedance Amplifier (TIA) and a Limiting Amplifier (LA). This thesis proposes the study and implementation of one of these blocks (LA), as the main focus, as well as the analysis and design of all three other blocks. The two major design constraints regarding the LA are the bandwidth and minimising its power consumption, which were overcome by using two bandwidth enhancement techniques. The circuit yields a bandwidth of 4:8GHz with a power consumption under 19mW. Another fundamental block is the Output Buffer. The major request for this block was maintaining relatively low transition times and improving the signal’s integrity. It has a differential output swing around 400mV with Pre-emphasis levels larger than 130%. The third block is the Received Signal Strength Indicator (RSSI). From a system point of view it is useful to have a measure of the input signal’s power so that the communication channel is used in its full potential. With a power consumption smaller than 600μW the RSSI presents an input dynamic range larger than 50 dB. The fourth block implements a Squelch function, in order to suppress unwanted output toggling due to noise. All these elements were developed in a TSMC 65nm CMOS process with a 1:2V supply voltage

Analog baseband circuits for sensor systems

This thesis is composed of six publications and an overview of the research topic, which also summarizes the work. The research presented in this thesis focuses on research into analog baseband circuits for sensor systems. The research is divided into three different topics: the integration of analog baseband circuits into a radio receiver for sensor applications; the integration of an ΔΣ modulator A/D converter into a GSM/WCDMA radio receiver for mobile phones, and the integration of algorithmic A/D converters for a capacitive micro-accelerometer interface. All the circuits are implemented using deep sub-micron CMOS technologies. The work summarizes the design of different blocks for sensor systems. The research into integrated analog baseband circuits for a radio receiver focuses on a circuit structures with a very low power dissipation and that can be implemented using only standard CMOS technologies. The research into integrated ΔΣ modulator A/D converter design for a GSM/WCDMA radio receiver for mobile phones focuses on the implications for analog circuit design emerging from using a very deep sub-micron CMOS process. Finally, in the research into algorithmic A/D converters for a capacitive microaccelerometer interface, new ways of achieving a good performance with low power dissipation, while also minimizing the silicon area of the integrated A/D converter are introduced

Ultra-low power receivers for wireless sensor networks

In wireless sensor network applications, low-power operation of the wireless receiver is critical. To address this need an ultra-low power Binary Frequency Shift Keying (BFSK) receiver using the super-regenerative architecture is developed. A prototype receiver is built and tested for operation in the 900 MHz ISM band. Lab measurements show power consumption as low as 244 μW with a sensitivity of -84 dBm while operating at 250 kbps. A second test chip designed to operate at 2.4 GHz improves on the previous design by adding full digital control and calibration. The 2.4 GHz receiver consumes 215 μW while operating at 250 kbps and shows a 12 dB improvement in sensitivity over the original design. The entire receiver has an energy consumption of only 0.175 nJ/b while operating at 2 Mbps

A Fully Implantable Opto-Electro Closed-Loop Neural Interface for Motor Neuron Disease Studies

This paper presents a fully implantable closed-loop device for use in freely moving rodents to investigate new treatments for motor neuron disease. The 0.18 µm CMOS integrated circuit comprises 4 stimulators, each featuring 16 channels for optical and electrical stimulation using arbitrary current waveforms at frequencies from 1.5 Hz to 50 kHz, and a bandwidth programmable front-end for neural recording. The implant uses a Qi wireless inductive link which can deliver >100 mW power at a maximum distance of 2 cm for a freely moving rodent. A backup rechargeable battery can support 10 mA continuous stimulation currents for 2.5 hours in the absence of an inductive power link. The implant is controlled by a graphic user interface with broad programmable parameters via a Bluetooth low energy bidirectional data telemetry link. The encapsulated implant is 40 mm × 20 mm × 10 mm. Measured results are presented showing the electrical performance of the electronics and the packaging method

Advanced Trends in Wireless Communications

Physical limitations on wireless communication channels impose huge challenges to reliable communication. Bandwidth limitations, propagation loss, noise and interference make the wireless channel a narrow pipe that does not readily accommodate rapid flow of data. Thus, researches aim to design systems that are suitable to operate in such channels, in order to have high performance quality of service. Also, the mobility of the communication systems requires further investigations to reduce the complexity and the power consumption of the receiver. This book aims to provide highlights of the current research in the field of wireless communications. The subjects discussed are very valuable to communication researchers rather than researchers in the wireless related areas. The book chapters cover a wide range of wireless communication topics

Enhancing Digital Controllability in Wideband RF Transceiver Front-Ends for FTTx Applications

Enhancing the digital controllability of wideband RF transceiver front-ends helps in widening the range of operating conditions and applications in which such systems can be employed. Technology limitations and design challenges often constrain the extensive adoption of digital controllability in RF front-ends. This work focuses on three major aspects associated with the design and implementation of a digitally controllable RF transceiver front-end for enhanced digital control. Firstly, the influence of the choice of semiconductor technology for a system-on-chip integration of digital gain control circuits are investigated. The digital control of gain is achieved by utilizing step attenuators that consist of cascaded switched attenuation stages. A design methodology is presented to evaluate the influence of the chosen technology on the performance of the three conventionally used switched attenuator topologies for desired attenuation levels, and the constraints that the technology suitable for high amplification places on the attenuator performance are examined. Secondly, a novel approach to the integrated implementation of gain slope equalization is presented, and the suitability of the proposed approach for integration within the RF front-end is verified. Thirdly, a sensitivity-aware implementation of a peak power detector is presented. The increased employment of digital gain control also increases the requirements on the sensitivity of the power detector employed for adaptive power and gain control. The design, implementation, and measurement results of a state-of-the-art wideband power detector with high sensitivity and large dynamic range are presented. The design is optimized to provide a large offset cancellation range, and the influence of offset cancellation circuits on the sensitivity of the power detector is studied. Moreover, design considerations for high sensitivity performance of the power detector are investigated, and the noise contributions from individual sub-circuits are evaluated. Finally, a wideband RF transceiver front-end is realized using a commercially available SiGe BiCMOS technology to demonstrate the enhancements in the digital controllability of the system. The RF front-end has a bandwidth of 500 MHz to 2.5 GHz, an input dynamic range of 20 dB, a digital gain control range larger than 30 dB, a digital gain slope equalization range from 1.49 dB/GHz to 3.78 dB/GHz, and employs a power detector with a sensitivity of -56 dBm and dynamic range of 64 dB. The digital control in the RF front-end is implemented using an on-chip serial-parallel-interface (SPI) that is controlled by an external micro-controller. A prototype implementation of the RF front-end system is presented as part of an RFIC intended for use in optical transceiver modules for fiber-to-the-x applications