Directed Placement for mVLSI Devices

Continuous-flow microfluidic devices based on integrated channel networks are becoming increasingly prevalent in research in the biological sciences. At present, these devices are physically laid out by hand by domain experts who understand both the underlying technology and the biological functions that will execute on fabricated devices. The lack of a design science that is specific to microfluidic technology creates a substantial barrier to entry. To address this concern, this article introduces Directed Placement, a physical design algorithm that leverages the natural "directedness" in most modern microfluidic designs: fluid enters at designated inputs, flows through a linear or tree-based network of channels and fluidic components, and exits the device at dedicated outputs. Directed placement creates physical layouts that share many principle similarities to those created by domain experts. Directed placement allows components to be placed closer to their neighbors compared to existing layout algorithms based on planar graph embedding or simulated annealing, leading to an average reduction in laid-out fluid channel length of 91% while improving area utilization by 8% on average. Directed placement is compatible with both passive and active microfluidic devices and is compatible with a variety of mainstream manufacturing technologies

Printed Circuit Board (PCB) design process and fabrication

This module describes main characteristics of Printed Circuit Boards (PCBs). A brief history of PCBs is introduced in the first chapter. Then, the design processes and the fabrication of PCBs are addressed and finally a study case is presented in the last chapter of the module.Peer ReviewedPostprint (published version

Skybridge-3D-CMOS: A Fine-Grained Vertical 3D-CMOS Technology Paving New Direction for 3D IC

2D CMOS integrated circuit (IC) technology scaling faces severe challenges that result from device scaling limitations, interconnect bottleneck that dominates power and performance, etc. 3D ICs with die-die and layer-layer stacking using Through Silicon Vias (TSVs) and Monolithic Inter-layer Vias (MIVs) have been explored in recent years to generate circuits with considerable interconnect saving for continuing technology scaling. However, these 3D IC technologies still rely on conventional 2D CMOS’s device, circuit and interconnect mindset showing only incremental benefits while adding new challenges reliability issues, robustness of power delivery network design and short-channel effects as technology node scaling. Skybridge-3D-CMOS (S3DC) is a fine-grained 3D IC fabric that uses vertically-stacked gates and 3D interconnections composed on vertical nanowires to yield orders of magnitude benefits over 2D ICs. This 3D fabric fully uses the vertical dimension instead of relying on a multi-layered 2D mindset. Its core fabric aspects including device, circuit-style, interconnect and heat-extraction components are co-architected considering the major challenges in 3D IC technology. In S3DC, the 3D interconnections provide greater routing capacity in both vertical and horizontal directions compared to conventional 3D ICs, which eliminates the routability issue in conventional 3D IC technology while enabling ultra-high density design and significant benefits over 2D. Also, the improved vertical routing capacity in S3DC is beneficial for achieving robust and high-density power delivery network (PDN) design while conventional 3D IC has design issues in PDN design due to limited routing resource in vertical direction. Additionally, the 3D gate-all-around transistor incorporating with 3D interconnect in S3DC enables significant SRAM design benefits and good tolerance of process variation compared to conventional 3D IC technology as well as 2D CMOS. The transistor-level (TR-L) monolithic 3D IC (M3D) is the state-of-the-art monolithic 3D technology which shows better benefits than other M3D approaches as well as the TSV-based 3D IC approach. The S3DC is evaluated in large-scale benchmark circuits with comparison to TR-L M3D as well as 2D CMOS. Skybridge yields up to 3x lower power against 2D with no routing congestion in benchmark circuits while TR-L M3D only has up-to 22% power saving with severe routing congestions in the design. The PDN design in S3DC show

Vibration Alert Bracelet for Notification of the Visually and Hearing Impaired

This paper presents the prototype of an electronic vibration bracelet designed to help the visually and hearing impaired to receive and send emergency alerts. The bracelet has two basic functions. The first function is to receive a wireless signal and respond with a vibration to alert the user. The second function is implemented by pushing one button of the bracelet to send an emergency signal. We report testing on a prototype system formed by a mobile application and two bracelets. The bracelets and the application form a complete system intended to be used in retirement apartment communities. However, the system is flexible and could be expanded to add new features or to serve as a research platform for gait analysis and location services. The medical and professional potential of the proposed system is that it offers a simple, modular, and cost-effective alternative to all the existing medical devices with similar functionality currently on the market. The proposed system has an educational potential as well: it can be used as a starting point for capstone projects and demonstration purposes in schools to attract students to STEM disciplines

Soft-Error Rate of Advanced SRAM Memories: Modeling and Monte Carlo Simulation

International audienc

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Piezoelectric Transformer and Hall-Effect Based Sensing and Disturbance Monitoring Methodology for High-Voltage Power Supply Lines

Advancements in relaying algorithms have led to an accurate and robust protection system widely used in power distribution. However, in low power sections of relaying systems, standard voltage and current measurement techniques are still used. These techniques have disadvantages like higher cost, size, electromagnetic interference, resistive losses and measurement errors and hence provide a number of opportunities for improvement and integration. We present a novel microsystem methodology to sense low-power voltage and current signals and detect disturbances in high-voltage power distribution lines. The system employs dual sensor architecture that consists of a piezoelectric transformer in combination with Hall-effect sensor, used to detect the disturbances whose harmonics are in the kHz frequency range. Our numerical analysis is based on three-dimensional finite element models of the piezoelectric transformer (PT) and the principle of Hall-effect based “Integrated Magnetic Concentrator (IMC)” sensor. This model is verified by using experimental data recorded in the resonant frequency and low frequency regions of operation of PT for voltage sensing. Actual measurements with the commercial IMC sensor too validate the modelling results. These results describe a characteristic low frequency behaviour of rectangular piezoelectric transformer, which enables it to withstand voltages as high as 150V. In the frequency range of 10Hz to 250Hz, the PT steps down 10-150V input with a linearity of ±1%. The recorded group delay data shows that propagation delay through PT reduces to few microseconds above 1kHz input signal frequency. Similarly, the non-intrusive current sensor detects current with a response time of 8μs and converts the current into corresponding output voltage. These properties, in addition to frequency spectrum of voltage and current input signals, have been used to develop a signal processing and fault detection system for two real-time cases of faults to produce a 6-bit decision logic capable of detecting various types of line disturbances in less than 3ms of delay