CMOS Front-End Circuits in 45-nm SOI Suitable for Modular Phased-Array 60-GHz Radios

Next Fifth-generation (5G) wireless technologies enabling ultra-wideband spectrum availability and increased system capacity can achieve multi-gigabit/s (Gbps) data rates suitable for ultra-high-speed internet access around the 60-GHz band (i.e., Wi-Gig Technology). This mm-wave band is unlicensed and experiences high propagation power losses. Therefore, it is suitable for short-range communications and requires antenna arrays to satisfy the link budget requirements. Half-duplex reconfigurable phased-array transceivers require wideband, low-cost, highly integrated front-end circuits such as bilateral RF switches, low-noise/power amplifiers, passive RF splitters/combiners, and phase shifters implemented in deep sub-micron CMOS. In this dissertation, analysis, design, and verification of essential CMOS front-end components are covered and fabricated in GlobalFoundries 45-nm RF-SOI CMOS technology. Firstly, a fully-differential, single-pole, single-throw (SPST) switch capable of high isolation in broadband CMOS transceivers is described. The SPST switch realizes better than 50-dB isolation (ISO) across DC to 43 GHz while maintaining an insertion loss (IL) below 3 dB. Measured RF input power for 1-dB compression (IP1dB) of the IL is +19.6 dBm, and the measured input third-order intercept point (IIP3) is +30.4 dBm (both assuming differential inputs at 20 GHz). The prototype has an active area of 0.0058 mm^2. Secondly, a single-pole double-throw (SPDT) switch is implemented using the SPST concept by using a balun to convert the shared differential path to a single-ended antenna port. The SPDT simulations predict less than 3.5-dB IL and greater than 40-dB ISO across 55 to 65 GHz frequency band. An IP1dB of +21 dBm is expected from large-signal simulations. The prototype has an active area of 0.117 mm^2. Thirdly, a fully-differential switched-LC topology adopted with slow-wave artificial transmission line concept, and phase inversion network is described for a 360-degree phase shift range with 11.25-degree phase resolution. The average IL of the complete phase shifter is 5.3 dB with less than 1-dB rms IL error. Furthermore, the IP1dB of the phase shifter is +16 dBm. The prototype has an active area of 0.245 mm^2. Lastly, a fully-differential, 2-stage, common-source (CS) low-noise amplifier (LNA) is developed with wideband matching from 57.8 GHz to 67 GHz, a maximum simulated forward power gain of 20.8 dB, and a minimum noise figure of 3.07 dB. The LNA consumes 21 mW and predicts an OP1dB of 4.8 dBm from the 1-V supply. The LNA consumes an active area of 0.028 mm^2

Design and Analysis of Low-power Millimeter-Wave SiGe BiCMOS Circuits with Application to Network Measurement Systems

Interest in millimeter (mm-) wave frequencies covering the spectrum of 30-300 GHz has been steadily increasing. Advantages such as larger absolute bandwidth and smaller form-factor have made this frequency region attractive for numerous applications, including high-speed wireless communication, sensing, material science, health, automotive radar, and space exploration. Continuous development of silicon-germanium heterojunction bipolar transistor (SiGe HBT) and associated BiCMOS technology has achieved transistors with fT/fmax of 505/720 GHz and integration with 55 nm CMOS. Such accomplishment and predictions of beyond THz performance have made SiGe BiCMOS technology the most competitive candidate for addressing the aforementioned applications. Especially for mobile applications, a critical demand for future mm-wave applications will be low DC power consumption (Pdc), which requires a substantial reduction of supply voltage and current. Conventionally, reducing the supply voltage will lead to HBTs operating close to or in the saturation region, which is typically avoided in mm-wave circuits due to expectated performance degradation and often inaccurate models. However, due to only moderate speed reduction at the forward-biased base-collector voltage (VBC) up to 0.5 V and the accuracy of the compact model HICUM/L2 also in saturation, low-power mm-wave circuits with SiGe HBTs operating in saturation offer intriguing benefits, which have been explored in this thesis based on 130 nm SiGe BiCMOS technologies: • Different low-power mm-wave circuit blocks are discussed in detail, including low-noise amplifiers (LNAs), down-conversion mixers, and various frequency multipliers covering a wide frequency range from V-band (50-75 GHz) to G-band (140-220 GHz). • Aiming at realizing a better trade-off between Pdc and RF performance, a drastic decrease in supply voltage is realized with forward-biased VBC, forcing transistors of the circuits to operate in saturation. • Discussions contain the theoretical analysis of the key figure of merits (FoMs), topology and bias selection, device sizing, and performance enhancement techniques. • A 173-207 GHz low-power amplifier with 23 dB gain and 3.2 mW Pdc, and a 72-108 GHz low-power tunable amplifier with 10-23 dB gain and 4-21 mW Pdc were designed. • A 97 GHz low-power down-conversion mixer was presented with 9.6 dB conversion gain (CG) and 12 mW Pdc. • For multipliers, a 56-66 GHz low-power frequency quadrupler with -3.6 dB peak CG and 12 mW Pdc, and a 172-201 GHz low-power frequency tripler with -4 dB peak CG and 10.5 mW Pdc were realized. By cascading these two circuits, also a 176-193 GHz low-power ×12 multiplier was designed, achieving -11 dBm output power with only 26 mW Pdc. • An integrated 190 GHz low-power receiver was designed as one receiving channel of a G-band frequency extender specifically for a VNA-based measurement system. Another goal of this receiver is to explore the lowest possible Pdc while keeping its highly competitive RF performance for general applications requiring a wide LO tuning range. Apart from the low-power design method of circuit blocks, the careful analysis and distribution of the receiver FoMs are also applied for further reduction of the overall Pdc. Along this line, this receiver achieved a peak CG of 49 dB with a 14 dB tunning range, consuming only 29 mW static Pdc for the core part and 171 mW overall Pdc, including the LO chain. • All designs presented in this thesis were fabricated and characterized on-wafer. Thanks to the accurate compact model HICUM/L2, first-pass access was achieved for all circuits, and simulation results show excellent agreement with measurements. • Compared with recently published work, most of the designs in this thesis show extremely low Pdc with highly competitive key FoMs regarding gain, bandwidth, and noise figure. • The observed excellent measurement-simulation agreement enables the sensitivity analysis of each design for obtaining a deeper insight into the impact of transistor-related physical effects on critical circuit performance parameters. Such studies provide meaningful feedback for process improvement and modeling development.:Table of Contents Kurzfassung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of symbols and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Technology 7 2.1 Fabrication Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 SiGe HBT performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 B11HFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 SG13G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.4 SG13D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Commonly Used Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Grounded-sidewall-shielded microstrip line . . . . . . . . . . . . . . . . . . 12 2.2.2 Zero-impedance Transmission Line . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.3.1 Active Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.3.2 Passive Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Low-power Low-noise Amplifiers 25 3.1 173-207 GHz Ultra-low-power Amplifier . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.1 Topology Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.2 Bias Dependency of the Small-signal Performance . . . . . . . . . . . . . 27 3.1.2.1 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1.2.2 Bias vs Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.2.3 Bias vs Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.2.4 Bias vs Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.3 Bias selection and Device sizing . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.1 Bias Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.2 Device Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1.4 Performance Enhancement Technologies . . . . . . . . . . . . . . . . . . . 41 3.1.4.1 Gm-boosting Inductors . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.4.2 Stability Enhancement . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.4.3 Noise Improvement . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1.5 Circuit Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.1 Layout Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.2 Inductors Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.5.3 Dual-band Matching Network . . . . . . . . . . . . . . . . . . . 48 3.1.5.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.6 Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2 72-108 GHz Low-Power Tunable Amplifier . . . . . . . . . . . . . . . . . . . . . . 55 3.2.1 Configuration, Sizing, and Bias Tuning Range . . . . . . . . . . . . . . . . 55 3.2.2 Regional Matching Network . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.1 Impedance Variation . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.2 Regional Matching Network Design . . . . . . . . . . . . . . . . 60 3.2.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4 Low-power Down-conversion Mixers 73 4.1 97 GHz Low-power Down-conversion Mixer . . . . . . . . . . . . . . . . . . . . . 74 4.1.1 Mixer Design and Implementation . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.1 Mixer Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.2 Bias Selection and Device Sizing . . . . . . . . . . . . . . . . . . 77 4.1.1.3 Mixer Implementation . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.2 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.1 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5 Low-power Multipliers 87 5.1 General Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.2 56-66 GHz Low-power Frequency Quadrupler . . . . . . . . . . . . . . . . . . . . 89 5.3 172-201 GHz Low-power Frequency Tripler . . . . . . . . . . . . . . . . . . . . . 93 5.4 176-193 GHz Low-power ×12 Frequency Multiplier . . . . . . . . . . . . . . . . . 96 5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6 Low-power Receivers 101 6.1 Receiver Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2 LO Chain (×12) Integrated 190 GHz Low-Power Receiver . . . . . . . . . . . . . 104 6.2.1 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2.2 Low-power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2.3 Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.1 LNA and LO DA . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.2 Tunable Mixer and IF BA . . . . . . . . . . . . . . . . . . . . . 111 6.2.3.3 65 GHz (V-band) Quadrupler . . . . . . . . . . . . . . . . . . . 116 6.2.3.4 G-band Tripler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.4 Receiver Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . 123 6.2.5 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.2.6 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7 Conclusions 133 7.1 Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.2 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Bibliography 135 List of Figures 149 List of Tables 157 A Derivation of the Gm 159 A.1 Gm of standard cascode stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 A.2 Gm of cascode stage with Lcas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 A.3 Gm of cascode stage with Lb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 B Derivation of Yin in the stability analysis 163 C Derivation of Zin and Zout 165 C.1 Zin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 C.2 Zout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 D Derivation of the cascaded oP1dB 169 E Table of element values for the designed circuits 17

Ultra Small Antenna and Low Power Receiver for Smart Dust Wireless Sensor Networks

Wireless Sensor Networks have the potential for profound impact on our daily lives. Smart Dust Wireless Sensor Networks (SDWSNs) are emerging members of the Wireless Sensor Network family with strict requirements on communication node sizes (1 cubic centimeter) and power consumption (< 2mW during short on-states). In addition, the large number of communication nodes needed in SDWSN require highly integrated solutions. This dissertation develops new design techniques for low-volume antennas and low-power receivers for SDWSN applications. In addition, it devises an antenna and low noise amplifier co-design methodology to increase the level of design integration, reduce receiver noise, and reduce the development cycle. This dissertation first establishes stringent principles for designing SDWSN electrically small antennas (ESAs). Based on these principles, a new ESA, the F-Inverted Compact Antenna (FICA), is designed at 916MHz. This FICA has a significant advantage in that it uses a small-size ground plane. The volume of this FICA (including the ground plane) is only 7% of other state-of-the-art ESAs, while its efficiency (48.53%) and gain (-1.38dBi) are comparable to antennas of much larger dimensions. A physics-based circuit model is developed for this FICA to assist system level design at the earliest stage, including optimization of the antenna performance. An antenna and low noise amplifier (LNA) co-design method is proposed and proven to be valid to design low power LNAs with the very low noise figure of only 1.5dB. To reduce receiver power consumption, this dissertation proposes a novel LNA active device and an input/ouput passive matching network optimization method. With this method, a power efficient high voltage gain cascode LNA was designed in a 0.13um CMOS process with only low quality factor inductors. This LNA has a 3.6dB noise figure, voltage gain of 24dB, input third intercept point (IIP3) of 3dBm, and power consumption of 1.5mW at 1.0V supply voltage. Its figure of merit, using the typical definition, is twice that of the best in the literature. A full low power receiver is developed with a sensitivity of -58dBm, chip area of 1.1mm2, and power consumption of 2.85mW

ANALYSIS AND DESIGN OF SILICON-BASED MILLIMETER-WAVE AMPLIFIERS

Ph.DDOCTOR OF PHILOSOPH

Millimeter-Wave Band Pass Distributed Amplifier for Low-Cost Active Multi-Beam Antennas

Recently, there have been a great interest in the millimeter-wave (mmW) and terahertz (THz) bands due to the unique features they provide for various applications. For example, the mmW is not significantly affected by the atmospheric constraints and it can penetrate through clothing and other dielectric materials. Therefore, it is suitable for a vast range of imaging applications such as vision, safety, health, environmental studies, security and non-destructive testing. Millimeter-wave imaging systems have been conventionally used for high end applications implementing sophisticated and expensive technologies. Recent advancements in the silicon integrated and low loss material passive technologies have created a great opportunity to study the feasibility of low cost mmW imaging systems. However, there are several challenges to be addressed first. Examples are modeling of active and passive devices and their low performance, highly attenuated channel and poor signal to noise ratio in the mmW. The main objective of this thesis is to investigate and develop new technologies enabling cost-effective implementation of mmW and sub-mmW imaging systems. To achieve this goal, an integrated active Rotman lens architecture is proposed as an ultimate solution to combine the unique properties of a Rotman lens with the superiority of CMOS technology for fabrication of cost effective integrated mmW systems. However, due to the limited sensitivity of on-chip detectors in the mmW, a large number of high gain, wide-band and miniaturized mmW Low Noise Amplifiers (LNA) are required to implement the proposed integrated Rotman lens architecture. A unique solution presented in this thesis is the novel Band Pass Distributed Amplifier (BPDA) topology. In this new topology, by short circuiting the line terminations in a Conventional Distributed Amplifier (CDA), standing waves are created in its artificial transmission lines. Conventionally, standing waves are strongly avoided by carefully matching these lines to 50 Ω in order to prevent instability of the amplifier. This causes that a large portion of the signal be absorbed in these resistive terminations. In this thesis, it is shown that due to presence of highly lossy parasitics of CMOS transistor at the mmW the amplifier stability is inherently achieved. Moreover, by eliminating these lossy and noise terminations in the CDA, the amplifier gain is boosted and its noise figure is reduced. In addition, a considerable decrease in the number of elements enables low power realization of many amplifiers in a small chip area. Using the lumped element model of the transistor, the transfer function of a single stage BPDAs is derived and compared to its conventional counter part. A methodology to design a single stage BPDA to achieve all the design goals is presented. Using the presented design guidelines, amplifiers for different mmW frequencies have been designed, fabricated and tested. Using only 4 transistors, a 60 GHz amplifier is fabricated on a very small chip area of 0.105 mm2 by a low-cost 130 nm CMOS technology. A peak gain of 14.7 dB and a noise figure of 6 dB are measured for this fabricated amplifier. oreover, it is shown that by further circuit optimization, high gain amplification can be realized at frequencies above the cut-off frequency of the transistor. Simulations show 32 and 28 dB gain can be obtained by implementing only 6 transistors using this CMOS technology at 60 and 77 GHz. A 4-stage 85 GHz amplifier is also designed and fabricated and a measured gain of 10 dB at 82 GHz is achieved with a 3 dB bandwidth of 11 GHz from 80 to 91 GHz. A good agreement between the simulated and measured results verifies the accuracy of the design procedure. In addition, a multi-stage wide-band BPDA has been designed to show the ability of the proposed topology for design of wide band mmW amplifiers using the CMOS technology. Simulated gain of 20.5 dB with a considerable 3 dB bandwidth of 38 GHz from 30 to 68 GHz is achieved while the noise figure is less than 6 dB in the whole bandwidth. An amplifier figure of merit is defined in terms of gain, noise figure, chip area, band width and power consumption. The results are compared to those of the state of the art to demonstrate the advantages of the proposed circuit topology and presented design techniques. Finally, a Rotman lens is designed and optimized by choosing a very small Focal Lens Ratio (FL), and a high measured efficiency of greater than 30% is achieved while the lens dimensions are less than 6 mm. The lens is designed and implemented using a low cost Alumina substrate and conventional microstrip lines to ease its integration with the active parts of the system.1 yea

TOWARDS LOW NOISE, HIGH POWER AND EFFICIENCY MM-WAVE AND TERAHERTZ CIRCUIT DESIGN

Mm-wave and terahertz frequency range is gaining vast attention in recent years due to attractive applications in various areas including spectroscopy, imaging, security and high data-rare communication. All these systems require high performance circuits for power generation and amplification. In recent years, many amplifiers and oscillators have been fabricated in SiGe and CMOS processes to show the feasibility of implementing these systems in this frequency range. Despite all the efforts and ideas employed to enhance the performance of these blocks, there is still a long way to go to achieve reasonably high performance amplifiers and signal sources at mm-wave and terahertz frequencies. The main challenge comes from the activity degradation of the transistors, high loss in the passives and high noise in the active and passive devices at this frequency range. In this work, new systematic design methods for low noise and highgain amplifiers and high power and efficiency oscillators at mm-wave and terahertz frequencies are presented. Chapter 1 reviews the basic concepts of the two-port networks such as stability, activity, power gains and noise parameters. These subjects are vastly used in the next chapters of this work when presenting the new methods for high frequency circuit design. In chapter 2, a new convex stability region is presented based on which, a systemic amplifier design method beyond fmax/2 is proposed which moves the network toward the high gain region using optimum passive embeddings. This method is capable of considering modeling errors of the components during the design process which results in a robust, stable and high gain amplifier. Employing this method, a three stage amplifier working at 173 GHz is designed and implemented in a 130 nm SiGe process which shows 18.5 dB gain, 8.2 GHz 3-dB bandwidth and 0.9 dBm saturated output power in the measurement. A new FoM is defined to fairly compare different amplifiers fabricatedindifferentprocesseswhichtargetsthecapabilityofthedesignmethodinextracting the power amplification potential of the active device. This amplifier achieves the highest FoM among all reported state of the arts works above fmax/2 in SiGe/CMOS processeswhichshowstheefficacyoftheproposedmethodinfullyutilizingtheprocess capabilities in amplifier design. In chapter 3, high frequency LNA is targeted and a systematic method to design low noise and high gain amplifier beyond fT/2 is presented. To achieve this goal, noise measure of the proposed structure becomes minimum employing optimum passive embeddings while the stability of the circuit is assured using the convex stability region derived in chapter 2. The guidelines and required noise and power equations to complete the systematic LNA design are derived and presented in this chapter. Employing this method,a 91 GHz LNA with 5.6dB noise figure,9.7 dB gain and 6.3 mW dc power consumption is implemented in a 130nm SiGe process. Comparing these results with the state of the arts using the proposed FoM that takes the process and power consumption into account justifies the effectiveness of this design method in fully utilizing low noise and high power generation capability of the process. A design methodology for high power mm-wave VCO design is presented in chapter 4. Using the complete passive embeddings including the load, the power gain from the input of the active device to the load is maximized which results in an oscillator with high power at the output and significantly improved DC-to-RF efficiency. In addition, the proposed structure is capable of providing sufficient tuning range which is an important factor in mm-wave source design and applications. A VCO working at 110 GHz is designed and implemented in a 55 nm SiGe process employing this method which shows 6.3 dBm peak output power, 20.9% DC-to-RF efficiency and 5.2% tuning range. This VCO achieves highest peak output power in F and D band (90 GHz to 170 GHz) and highest DC-to-RF efficiency in frequencies below fmax/2 among all reported mm-wave oscillators in SiGe/CMOS processes. Chapter 5 represents a new design method for high power and efficiency harmonic oscillator. This method exploits different mechanism to enhance the fundamental oscillator performance, increasing the harmonic power generation in the active device and effectively delivering the generated harmonic power to the load using various passive embeddings in a cross-coupled structure. Capacitive degeneration is employed to shape Gm of the structure. Inductive embeddings at the base of the transistors are utilized to provide sufficient voltage gain and increase harmonic current generation in the active device. The embeddings at the collector are used to maximize the output resistance of the structure which results in delivering majority of the generated current to the load. Employing this method, a 300 GHz harmonic oscillator is designed and implemented in a 130 nm SiGe process which shows 2.8 dBm peak output power and 4.5% DC-to-RF efficiency with 86.6 mW/mm2 power-area efficiency. Also, a harmonic VCO is implemented with 2.3 dBm peak output power, 3.5% DC-to-RF efficiency and 1.5% tuning range and 77.2 mW/mm2 power-area efficiency in the same process. This harmonic oscillator method significantly improves the power-area efficiency of high frequency signal sources and the designed oscillator achieves the highest power-area efficiency among all reported SiGe/CMOS oscillators working above 0.75 fmax

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Millimeter-Wave GaN Solid-State Arrays

Millimeter-wave applications above Ka-band have become increasingly important for both the military and commercial sector. With the overcrowded spectrum at lower microwave frequencies, more systems are demanding the use of unlicensed spectrum space at V-, W-band and beyond. Data communications for wireless links are requiring frequencies greater than 75 GHz to achieve high data rates up 80 Gbps. Scalable W-band phased arrays using silicon technology have been demonstrated for automotive radar, imaging and communication. Technologies such as Gallium-Nitride (GaN) have been pushing high-frequency performance with operating frequencies in the hundreds of GHz allowing the capability for solid-state high-power transmitters. General challenges forW-band high-power solid-state transmitters are achieving high effective radiated power (ERP) in a small footprint and with reasonable efficiency for space constrained applications. Recent advances in GaN technology with cutoff frequencies ft &gt; 150 GHz achieve power densities as highas 3W/mm at W-band. For very high-power applications many amplifiers are required to be combined and fed into an array for spatially coherently power combining. The need for multiple levels of power combining provides a trade off in terms of combining efficiency, heat dissipation, volume and co-design from the transistor to the radiating aperture. Each power amplifier (PA) module can have varying levels of power combining including device level within a monolithic microwave integrated circuit (MMIC) amplifier, thin-film and waveguided power combining, and spatial power combining to achieve the desired ERP. This thesis focuses on the design and analysis of millimeter-wave MMIC power amplifiers for high effective radiated power (ERP) using three GaN research processes in development by the industry. W-band PAs are presented and predict state-of-the-art output power. Analysis of power combining efficiency anddegradation in power combiners and phased arrays caused by GaN-on-SiC semiconductor process variations is presented.</p

Applications of MATLAB in Science and Engineering

The book consists of 24 chapters illustrating a wide range of areas where MATLAB tools are applied. These areas include mathematics, physics, chemistry and chemical engineering, mechanical engineering, biological (molecular biology) and medical sciences, communication and control systems, digital signal, image and video processing, system modeling and simulation. Many interesting problems have been included throughout the book, and its contents will be beneficial for students and professionals in wide areas of interest