Improved modeling of Coulomb effects in nanoscale Schottky-barrier FETs

We employ a novel multi-configurational self-consistent Green's function approach (MCSCG) for the simulation of nanoscale Schottky-barrier field-effect transistors. This approach allows to calculate the electronic transport with a seamless transition from the single-electron regime to room temperature field-effect transistor operation. The particular improvement of the MCSCG stems from a division of the channel system into a small subsystem of resonantly trapped states for which a many-body Fock space becomes feasible and a strongly coupled rest which can be treated adequately on a conventional mean-field level. The Fock space description allows for the calculation of few-electron Coulomb charging effects beyond mean-field. We compare a conventional Hartree non-equilibrium Green's function calculation with the results of the MCSCG approach. Using the MCSCG method Coulomb blockade effects are demonstrated at low temperatures while under strong nonequilibrium and room temperature conditions the Hartree approximation is retained

Doping-free complementary WSe2 circuit via van der Waals metal integration.

Two-dimensional (2D) semiconductors have attracted considerable attention for the development of ultra-thin body transistors. However, the polarity control of 2D transistors and the achievement of complementary logic functions remain critical challenges. Here, we report a doping-free strategy to modulate the polarity of WSe2 transistors using same contact metal but different integration methods. By applying low-energy van der Waals integration of Au electrodes, we observed robust and optimized p-type transistor behavior, which is in great contrast to the transistors fabricated on the same WSe2 flake using conventional deposited Au contacts with pronounced n-type characteristics. With the ability to switch majority carrier type and to achieve optimized contact for both electrons and holes, a doping-free logic inverter is demonstrated with higher voltage gain of 340, at the bias voltage of 5.5 V. Furthermore, the simple polarity control strategy is extended for realizing more complex logic functions such as NAND and NOR

X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories

Silicon-based Static Random Access Memories (SRAM) and digital Boolean logic have been the workhorse of the state-of-art computing platforms. Despite tremendous strides in scaling the ubiquitous metal-oxide-semiconductor transistor, the underlying \textit{von-Neumann} computing architecture has remained unchanged. The limited throughput and energy-efficiency of the state-of-art computing systems, to a large extent, results from the well-known \textit{von-Neumann bottleneck}. The energy and throughput inefficiency of the von-Neumann machines have been accentuated in recent times due to the present emphasis on data-intensive applications like artificial intelligence, machine learning \textit{etc}. A possible approach towards mitigating the overhead associated with the von-Neumann bottleneck is to enable \textit{in-memory} Boolean computations. In this manuscript, we present an augmented version of the conventional SRAM bit-cells, called \textit{the X-SRAM}, with the ability to perform in-memory, vector Boolean computations, in addition to the usual memory storage operations. We propose at least six different schemes for enabling in-memory vector computations including NAND, NOR, IMP (implication), XOR logic gates with respect to different bit-cell topologies $-$ the 8T cell and the 8$^+$T Differential cell. In addition, we also present a novel \textit{`read-compute-store'} scheme, wherein the computed Boolean function can be directly stored in the memory without the need of latching the data and carrying out a subsequent write operation. The feasibility of the proposed schemes has been verified using predictive transistor models and Monte-Carlo variation analysis.Comment: This article has been accepted in a future issue of IEEE Transactions on Circuits and Systems-I: Regular Paper

High-temperature microphone system

Pressure fluctuations in air or other gases in an area of elevated temperature are measured using a condenser microphone located in the area of elevated temperature and electronics for processing changes in the microphone capacitance located outside the area the area and connected to the microphone by means of high-temperature cable assembly. The microphone includes apparatus for decreasing the undesirable change in microphone sensitivity at high temperatures. The high temperature cable assembly operates as a half-wavelength transmission line in an AM carrier system and maintains a large temperature gradient between the two ends of the cable assembly. The processing electronics utilizes a voltage controlled oscillator for automatic tuning thereby increasing the sensitivity of the measuring apparatus