1,796 research outputs found
Integrated chaos generators
This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110
Infrastructure for Detector Research and Development towards the International Linear Collider
The EUDET-project was launched to create an infrastructure for developing and
testing new and advanced detector technologies to be used at a future linear
collider. The aim was to make possible experimentation and analysis of data for
institutes, which otherwise could not be realized due to lack of resources. The
infrastructure comprised an analysis and software network, and instrumentation
infrastructures for tracking detectors as well as for calorimetry.Comment: 54 pages, 48 picture
Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor
Due to the switch from CCD to CMOS technology, CMOS based image sensors have become
smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart
from the extensive set of applications requiring image sensors, the next technological
breakthrough in imaging would be to consolidate and completely shift the conventional CMOS
image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative
technology in the imaging field, allowing multiple silicon tiers with different functions to be
stacked on top of each other. The technology allows for an extreme parallelism of the pixel
readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked
image sensor, and the parallelism of the readout can remain constant at any spatial resolution of
the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor
array resolution.
The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked
image sensors, structured with parallel readout circuitries. The readout circuit’s key
requirements are low noise, speed, low-area (for higher parallelism), and low power.
A CMOS imaging review is presented through a short historical background, followed by the
description of the motivation, the research goals, and the work contributions. The fundamentals
of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features,
the essential building blocks, types of operation, as well as their physical characteristics and their
evaluation metrics. Following up on this, the document pays attention to the readout circuit’s
noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron
noise imagers. Lastly, the fabricated test CIS device performances are reported along with
conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future
work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores
CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que
requerem sensores de imagem, o próximo salto tecnológico no ramo dos sensores de imagem é
o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a
tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia
inovadora no campo dos sensores de imagem, permitindo vários planos de silício com diferentes
funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um
paralelismo extremo na leitura dos sinais vindos da matriz de píxeis. Além disso, num sensor de
imagem de planos de silício empilhados, os circuitos de leitura estão posicionados debaixo da
matriz de píxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer
resolução espacial, permitindo assim atingir um extremo baixo ruído e um alto debito de
imagens, virtualmente para qualquer resolução desejada.
O objetivo deste trabalho é o de desenhar circuitos de leitura de coluna de muito baixo ruído,
planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas
altamente paralelizadas. Os requisitos chave para os circuitos de leitura são de baixo ruído,
rapidez e pouca área utilizada, de forma a obter-se o melhor rácio.
Uma breve revisão histórica dos sensores de imagem CMOS é apresentada, seguida da
motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem
CMOS são também abordados para expor as suas características, os blocos essenciais, os tipos
de operação, assim como as suas características físicas e suas métricas de avaliação. No
seguimento disto, especial atenção é dada à teoria subjacente ao ruído inerente dos circuitos de
leitura e dos conversores de coluna, servindo para identificar os possíveis aspetos que dificultem
atingir a tão desejada performance de muito baixo ruído. Por fim, os resultados experimentais
do sensor desenvolvido são apresentados junto com possíveis conjeturas e respetivas conclusões,
terminando o documento com o assunto de empilhamento vertical de camadas de silício, junto
com o possível trabalho futuro
Review of Recent Trends
This work was partially supported by the European Regional Development Fund (FEDER), through the Regional Operational Programme of Centre (CENTRO 2020) of the Portugal 2020 framework, through projects SOCA (CENTRO-01-0145-FEDER-000010) and ORCIP (CENTRO-01-0145-FEDER-022141). Fernando P. Guiomar acknowledges a fellowship from “la Caixa” Foundation (ID100010434), code LCF/BQ/PR20/11770015. Houda Harkat acknowledges the financial support of the Programmatic Financing of the CTS R&D Unit (UIDP/00066/2020).MIMO-OFDM is a key technology and a strong candidate for 5G telecommunication systems. In the literature, there is no convenient survey study that rounds up all the necessary points to be investigated concerning such systems. The current deeper review paper inspects and interprets the state of the art and addresses several research axes related to MIMO-OFDM systems. Two topics have received special attention: MIMO waveforms and MIMO-OFDM channel estimation. The existing MIMO hardware and software innovations, in addition to the MIMO-OFDM equalization techniques, are discussed concisely. In the literature, only a few authors have discussed the MIMO channel estimation and modeling problems for a variety of MIMO systems. However, to the best of our knowledge, there has been until now no review paper specifically discussing the recent works concerning channel estimation and the equalization process for MIMO-OFDM systems. Hence, the current work focuses on analyzing the recently used algorithms in the field, which could be a rich reference for researchers. Moreover, some research perspectives are identified.publishersversionpublishe
Next-generation optical access networks based on Orthogonal Frequency Division Multiplexing
Orthogonal Frequency Division Multiplexing (OFDM) is a robust modulation and multiplexing format which is at the base of many present communication standards.
The interest of the OFDM application in optical fiber deployments is quite recent. As the next generation of Passive Optical Networks (NG-PONs) is envisioned, targeting greater capacity and user counts, the limitations of TDMA (Time Division Multiplexing Access) approaches to meet the expected increase in requirements becomes evident and therefore new technologies are being explored. Optical OFDMA is an emerging technology which can be a promising candidate.
The main goal of this Master Thesis is to study the problem of users multiplexing in access networks, using OFDM as a technology to transmit the user information data. This work has focused in the uplink study of the network, because it is the most challenging part of the network to design.
The studies have been conducted both in a theoretical way and also by simulating the targeted environments by means of a fiber optics transmission simulation tool. Virtual Photonics Integrated (VPI) is the software selected for the simulations. This tool is specially designed to simulate optical transmission system environments.
The analysis of the Optical Beat Interference, which is a critical impairment in optical carrier multiplexing schemes, is the most important part of the user
multiplexing study
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Nonreciprocal Wavefront Engineering with Time-Modulated Gradient Metasurfaces
We propose a paradigm to realize nonreciprocal wavefront engineering using time-modulated gradient metasurfaces. The essential building block of these surfaces is a subwavelength unit cell whose reflection coefficient oscillates at low frequency. We demonstrate theoretically and experimentally that such modulation permits tailoring the phase and amplitude of any desired nonlinear harmonic and determines the behavior of all other emerging fields. By appropriately adjusting the phase delay applied to the modulation of each unit cell, we realize time-modulated gradient metasurfaces that provide efficient conversion between two desired frequencies and enable nonreciprocity by (i) imposing drastically different phase gradients during the up/down conversion processes and (ii) exploiting the interplay between the generation of certain nonlinear surface and propagative waves. To demonstrate the performance and broad reach of the proposed platform, we design and analyze metasurfaces able to implement various functionalities, including beam steering and focusing, while exhibiting strong and angle-insensitive nonreciprocal responses. Our findings open an alternative direction in the field of gradient metasurfaces, in which wavefront control and magnetic-free nonreciprocity are locally merged to manipulate the scattered fields
High-Bandwidth Voltage-Controlled Oscillator based architectures for Analog-to-Digital Conversion
The purpose of this thesis is the proposal and implementation of data conversion
open-loop architectures based on voltage-controlled oscillators (VCOs) built with
ring oscillators (RO-based ADCs), suitable for highly digital designs, scalable to
the newest complementary metal-oxide-semiconductor (CMOS) nodes.
The scaling of the design technologies into the nanometer range imposes the
reduction of the supply voltage towards small and power-efficient architectures,
leading to lower voltage overhead of the transistors. Additionally, phenomena
like a lower intrinsic gain, inherent noise, and parasitic effects (mismatch between
devices and PVT variations) make the design of classic structures for ADCs more
challenging. In recent years, time-encoded A/D conversion has gained relevant
popularity due to the possibility of being implemented with mostly digital structures.
Within this trend, VCOs designed with ring oscillator based topologies
have emerged as promising candidates for the conception of new digitization
techniques.
RO-based data converters show excellent scalability and sensitivity, apart from
some other desirable properties, such as inherent quantization noise shaping and
implicit anti-aliasing filtering. However, their nonlinearity and the limited time
delay achievable in a simple NOT gate drastically limits the resolution of the converter,
especially if we focus on wide-band A/D conversion. This thesis proposes
new ways to alleviate these issues.
Firstly, circuit-based techniques to compensate for the nonlinearity of the ring
oscillator are proposed and compared to equivalent state-of-the-art solutions.
The proposals are designed and simulated in a 65-nm CMOS node for open-loop
RO-based ADC architectures. One of the techniques is also validated experimentally
through a prototype. Secondly, new ways to artificially increase the effective
oscillation frequency are introduced and validated by simulations. Finally, new
approaches to shape the quantization noise and filter the output spectrum of a
RO-based ADC are proposed theoretically. In particular, a quadrature RO-based
band-pass ADC and a power-efficient Nyquist A/D converter are proposed and
validated by simulations.
All the techniques proposed in this work are especially devoted for highbandwidth
applications, such as Internet-of-Things (IoT) nodes or maximally
digital radio receivers. Nevertheless, their field of application is not restricted to
them, and could be extended to others like biomedical instrumentation or sensing.El propósito de esta tesis doctoral es la propuesta y la implementación de arquitecturas
de conversión de datos basadas en osciladores en anillos, compatibles
con diseños mayoritariamente digitales, escalables en los procesos CMOS de fabricación
más modernos donde las estructuras digitales se ven favorecidas.
La miniaturización de las tecnologías CMOS de diseño lleva consigo la reducción
de la tensión de alimentación para el desarrollo de arquitecturas pequeñas
y eficientes en potencia. Esto reduce significativamente la disponibilidad de tensión
para saturar transistores, lo que añadido a una ganancia cada vez menor
de los mismos, ruido y efectos parásitos como el “mismatch” y las variaciones
de proceso, tensión y temperatura han llevado a que sea cada vez más complejo
el diseño de estructuras analógicas eficientes. Durante los últimos años la conversión
A/D basada en codificación temporal ha ganado gran popularidad dado
que permite la implementación de estructuras mayoritariamente digitales. Como
parte de esta evolución, los osciladores controlados por tensión diseñados con topologías
de oscilador en anillo han surgido como un candidato prometedor para
la concepción de nuevas técnicas de digitalización.
Los convertidores de datos basados en osciladores en anillo son extremadamente
sensibles (variación de frecuencia con respecto a la señal de entrada) así como
escalables, además de otras propiedades muy atractivas, como el conformado
espectral de ruido de cuantificación y el filtrado “anti-aliasing”. Sin embargo, su
respuesta no lineal y el limitado tiempo de retraso alcanzable por una compuerta
NOT restringen la resolución del conversor, especialmente para conversión A/D
en aplicaciones de elevado ancho de banda. Esta tesis doctoral propone nuevas
técnicas para aliviar este tipo de problemas.
En primer lugar, se proponen técnicas basadas en circuito para compensar el
efecto de la no linealidad en los osciladores en anillo, y se comparan con soluciones
equivalentes ya publicadas. Las propuestas se diseñan y simulan en tecnología
CMOS de 65 nm para arquitecturas en lazo abierto. Una de estas técnicas
presentadas es también validada experimentalmente a través de un prototipo.
En segundo lugar, se introducen y validan por simulación varias formas de incrementar
artificialmente la frecuencia de oscilación efectiva. Para finalizar, se
proponen teóricamente dos enfoques para configurar nuevas formas de conformación
del ruido de cuantificación y filtrado del espectro de salida de los datos
digitales. En particular, son propuestos y validados por simulación un ADC pasobanda
en cuadratura de fase y un ADC de Nyquist de gran eficiencia en potencia. Todas las técnicas propuestas en este trabajo están destinadas especialmente
para aplicaciones de alto ancho de banda, tales como módulos para el Internet
de las cosas o receptores de radiofrecuencia mayoritariamente digitales. A pesar
de ello, son extrapolables también a otros campos como el de la instrumentación
biomédica o el de la medición de señales mediante sensores.Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Juan Pablo Alegre Pérez.- Secretario: Celia López Ongil.- Vocal: Fernando Cardes Garcí
Disseny microelectrnic de circuits discriminadors de polsos pel detector LHCb
The aim of this thesis is to present a solution for implementing the front end system of the Scintillator Pad Detector (SPD) of the calorimeter system of the LHCb experiment that will start in 2008 at the Large Hadron Collider (LHC) at CERN. The requirements of this specific system are discussed and an integrated solution is presented, both at system and circuit level. We also report some methodological achievements. In first place, a method to study the PSRR (and any transfer function) in fully differential circuits taking into account the effect of parameter mismatch is proposed. Concerning noise analysis, a method to study time variant circuits in the frequency domain is presented and justified. This would open the possibility to study the effect of 1/f noise in time variants circuits. In addition, it will be shown that the architecture developed for this system is a general solution for front ends in high luminosity experiments that must be operated with no dead time and must be robust against ballistic deficit
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