Analysis of Residue Probability Density Function and Comparator Offset Error in Pipelined ADCs

This paper presents a new approach to analyze the convergence of residue probability density function (pdf) in pipelined ADCs. Compared to the previous approaches, in the proposed approach, in addition to the analysis of residue pdfs for different input densities, the analysis of the sub-ADC comparator offsets impact on output pdf is possible. Using Fourier analysis, it will be shown that the residue density converges to uniformity. In the half-bit redundant structure, residue pdf concentrates in the center half of the stage full-scale range and 6 dB of extra resolution can be gained. Also, the share of each stage in this resolution improvement is investigated. Examining the sub-ADC threshold offsets impact on residue pdfs, it is observed that with respect to the impact on converter additional resolution, the final stages offset errors are more significant than the first stages offsets

A novel digital background calibration technique for 16 bit SHA-less multibit pipelined ADC

In this paper, a high resolution of 16 bit and high speed of 125MS/s, multibit Pipelined ADC with digital background calibration is presented. In order to achieve low power, SHA-less front end is used with multibit stages. The first and second stages are used here as a 3.5 bit and the stages from third to seventh are of 2.5 bit and last stage is of 3-bit flash ADC. After bit alignment and truncation of total 19 bits, 16 bits are used as final digital output. To precise the remove linear gain error of the residue amplifier and capacitor mismatching error, a digital background calibration technique is used, which is a combination of signal dependent dithering (SDD) and butterfly shuffler. To improve settling time of residue amplifier, a special circuit of voltage separation is used. With the proposed digital background calibration technique, the spurious-free dynamic range (SFDR) has been improved to 97.74 dB @30 MHz and 88.9 dB @150 MHz, and the signal-to-noise and distortion ratio (SNDR) has been improved to 79.77 dB @ 30 MHz, and 73.5 dB @ 150 MHz. The implementation of the Pipelined ADC has been completed with technology parameters of 0.18μm CMOS process with 1.8 V supply. Total power consumption is 300 mW by the proposed ADC

Low power high speed and high accuracy design methodologies for pipeline Analog-to-Digital converters

Different aspects of power optimization of a high-speed, high-accuracy pipeline Analog-to-Digital Converters (ADCs) are considered to satisfy the current and future needs of portable communication devices. First power optimized design strategies for the amplifiers are introduced. Closed form expressions of power w.r.t settling requirements are presented to facilitate a fair comparison and selection of the amplifier structure. Next a new low offset dynamic comparator has been designed. Simulation based sensitivity analysis is performed to demonstrate the robustness of the new comparator with respect to stray capacitances, common mode voltage errors and timing errors. With simplified amplifier power model along with the use of dynamic comparators, a method to optimize the power consumption of a pipeline ADC with kT/C noise constraint is also developed. The total power dependence on capacitor scaling and stage resolution is investigated for a near-optimal solution.;After considering the power requirements of a pipeline ADC, design and statistical modeling of over-range protection requirements is investigated. Closed form statistical expressions for the over-range requirements are developed to assist in the allocation of the error budgets to different pipeline blocks. A new over-range protection algorithm is also developed that relaxes the amplifier design and power requirements.;Finally, two new CMOS Schmitt trigger designs are proposed which can be used as clock inputs for the pipeline ADC. In the new designs, sizing of the feedback inverters is used for independent trip point control. The new designs have also a modest reduction in sensitivity to process variations along with immunity to the kick-back noise without the addition of path delay

Design of a low power switched-capacitor pipeline analog-to-digital converter

An Analog to Digital Converter (ADC) is a circuit which converts an analog signal into digital signal. Real world is analog, and the data processed by the computer or by other signal processing systems is digital. Therefore, the need for ADCs is obvious. In this thesis, several novel designs used to improve ADCs operation speed and reduce ADC power consumption are proposed. First, a high speed switched source follower (SSF) sample and hold amplifier without feedthrough penalty is implemented and simulated. The SSF sample and hold amplifier can achieve 6 Bit resolution with sampling rate at 10Gs/s. Second, a novel rail-to-rail time domain comparator used in successive approximation register ADC (SAR ADC) is implemented and simulated. The simulation results show that the proposed SAR ADC can only consume 1.3 muW with a 0.7 V power supply. Finally, a prototype pipeline ADC is implemented and fabricated in an IBM 90nm CMOS process. The proposed design is validated using measurement on a fabricated silicon IC, and the proposed 10-bit ADC achieves a peak signal-to-noise- and-distortion-ratio (SNDR) of 47 dB. This SNDR translates to a figure of merit (FOM) of 2.6N/conversion-step with a 1.2 V power supply

Energy Efficient Pipeline ADCs Using Ring Amplifiers

Pipeline ADCs require accurate amplification. Traditionally, an operational transconductance amplifier (OTA) configured as a switched-capacitor (SC) amplifier performs such amplification. However, traditional OTAs limit the power efficiency of ADCs since they require high quiescent current for slewing and bandwidth. In addition, it is difficult to design low-voltage OTAs in modern, scaled CMOS. The ring amplifier is an energy efficient and high output swing alternative to an OTA for SC circuits which is basically a three-stage inverter amplifier stabilized in a feedback configuration. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. In this dissertation, three types of innovative ring amplifiers are presented and verified with state-of-the-art energy efficient pipeline ADCs. These new ring amplifiers overcome the limitations of the conventional ring amplifier and further improve energy efficiency. The first topic of this dissertation is a self-biased ring amplifier that makes the ring amplifier more practical and power efficient, while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. In addition, the ring amplifiers are also used as comparators in the 1.5b sub-ADCs by utilizing the unique characteristics of the ring amplifier. This removes the need for dedicated comparators in sub-ADCs, thus further reducing the power consumption of the ADC. The prototype 10.5b 100 MS/s comparator-less pipeline ADC with the self-biased ring amplifiers has measured SNDR, SNR and SFDR of 56.6 dB (9.11b), 57.5 dB and 64.7 dB, respectively, and consumes 2.46 mW, which results in Walden Figure-of-Merit (FoM) of 46.1 fJ/ conversion∙step. The second topic is a fully-differential ring amplifier, which solves the problems of single-ended ring amplifiers while maintaining the benefits of the single-ended ring amplifiers. This differential ring-amplifier is applied in a 13b 50 MS/s SAR-assisted pipeline ADC. Furthermore, an improved capacitive DAC switching method for the first stage SAR reduces the DAC linearity errors and switching energy. The prototype ADC achieves measured SNDR, SNR and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, and consumes 1 mW. This measured performance is equivalent to Walden and Schreier FoMs of 6.9 fJ/conversion∙step and 174.9 dB, respectively. Finally, a four-stage fully-differential ring amplifier improves the small-signal gain to over 90 dB without compromising speed. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. This is more area efficient than the conventional auto-zero noise folding reduction technique. A systematic mismatch free SAR CDAC layout method is also presented. The prototype 15b 100 MS/s calibration-free SAR-assisted pipeline ADC using the four-stage ring amplifier achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in Schreier FoM of 176.6 dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138759/1/yonglim_1.pd

A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude

High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip

With higher-level integration driven by increasingly complex digital systems and downscaling CMOS processes available, system-on-a-chip (SoC) is an emerging technology of low power, high cost effectiveness and high reliability and is exceedingly attractive for applications in high-speed data conversion wireless and wideband communication systems. This research presents a novel ADC comparator design methodology; the speed and performance of which is not restricted by the supply voltage reduction and device linearity deterioration in scaling-down CMOS processes. By developing a dynamic offset suppression technique and a circuit optimization method, the comparator can achieve a 3 dB frequency of 2 GHz in 130 nanometer (nm) CMOS process. Combining this new comparator design and a proposed pipelined thermometer-Gray- binary encoder designed by the DCVSPG logic, a high-speed, low-voltage clocked-digital- comparator (CDC) pipelined CMOS flash ADC architecture is proposed for wideband communication SoC. This architecture has advantages of small silicon area, low power, and low cost. Three CDC-based pipelined CMOS flash ADCs were implemented in 130 nm CMOS process and their experimental results are reported: 1. 4-b, 2.5-GSPS ADC: SFDR of 21.48-dB, SNDR of 15.99-dB, ENOB of 2.4-b, ERBW of 1-GHz, power of 7.9-mW, and area of 0.022-mm2. 2. 4-b, 4-GSPS ADC: SFDR of 25-dB, SNDR of 18.6-dB, ENOB of 2.8-b, ERBW of 2-GHz, power of 11-mW. 3. 6-b, 4-GSPS ADC: SFDR of 48-dB at a signal frequency of 11.72-MHz, SNDR of 34.43-dB, ENOB of 5.4-b, power of 28-mW. An application of the proposed CDC-based pipelined CMOS flash ADC is 1-GHz bandwidth, 2.5-GSPS digital receiver on a chip. To verify the performance of the receiver, a mixed-signal block-level simulation and verification flow was built in Cadence AMS integrated platform. The verification results of the digital receiver using a 4-b 2.5-GSPS CDC-based pipelined CMOS ADC, a 256-point, 12-point kernel function FFT and a frequency detection logic show that two tone signals up to 1125 MHz can be detected and discriminated. A notable contribution of this research is that the proposed ADC architecture and the comparator design with dynamic offset suppression and optimization are extremely suitable for future VDSM CMOS processes and make all-digital receiver SoC design practical

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

Accuracy enhancement techniques in low-voltage high-speed pipelined ADC design

Pipelined analog to digital converters (ADCs) are very important building blocks in many electronic systems such as high quality video systems, high performance digital communication systems and high speed data acquisition systems. The rapid development of these applications is driving the design of pipeline ADCs towards higher speed, higher dynamic range, lower power consumption and lower power supply voltage with the CMOS technology scaling. This trend poses great challenges to conventional pipelined ADC designs which rely on high-gain operational amplifiers (opamps) and well matched capacitors to achieve high accuracy. In this thesis, two novel accuracy improvement techniques to overcome the accuracy limit set by analog building blocks (opamps and capacitors) in the context of low-voltage and high-speed pipelined ADC design are presented. One is the time-shifted correlated double sampling (CDS) technique which addresses the finite opamp gain effect and the other is the radix-based background digital calibration technique which can take care of both finite opamp gain and capacitor mismatch. These methods are simple, easy to implement and power efficient. The effectiveness of the proposed techniques is demonstrated in simulation as well as in experiment. Two prototype ADCs have been designed and fabricated in 0.18μm CMOS technology as the experimental verification of the proposed techniques. The first ADC is a 1.8V 10-bit pipeline ADC which incorporated the time-shifted CDS technique to boost the effective gain of the amplifiers. Much better gain-bandwidth tradeoff in amplifier design is achieved with this gain boosting. Measurement results show total power consumption of 67mW at 1.8V when operating at 100MSPS. The SNR, SNDR and SFDR are 55dB, 54dB and 65dB respectively given a 1MHz input signal. The second one is a 0.9V 12-bit two-stage cyclic ADC which employed a novel correlation-based background calibration to enhance the linearity. The linearity limit set by the capacitor mismatches, finite opamp gain effects is exceeded. After calibration, the SFDR is improved by about 33dB and exceeds 80dB. The power consumption is 12mW from 0.9V supply when operating at 2MSPS