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    ์ดˆ๋ฏธ์„ธ ํšŒ๋กœ ์„ค๊ณ„๋ฅผ ์œ„ํ•œ ์ธํ„ฐ์ปค๋„ฅํŠธ์˜ ํƒ€์ด๋ฐ ๋ถ„์„ ๋ฐ ๋””์ž์ธ ๋ฃฐ ์œ„๋ฐ˜ ์˜ˆ์ธก

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    ํ•™์œ„๋…ผ๋ฌธ (๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ปดํ“จํ„ฐ๊ณตํ•™๋ถ€, 2021. 2. ๊น€ํƒœํ™˜.ํƒ€์ด๋ฐ ๋ถ„์„ ๋ฐ ๋””์ž์ธ ๋ฃฐ ์œ„๋ฐ˜ ์ œ๊ฑฐ๋Š” ๋ฐ˜๋„์ฒด ์นฉ ์ œ์กฐ๋ฅผ ์œ„ํ•œ ๋งˆ์Šคํฌ ์ œ์ž‘ ์ „์— ์™„๋ฃŒ๋˜์–ด์•ผ ํ•  ํ•„์ˆ˜ ๊ณผ์ •์ด๋‹ค. ๊ทธ๋Ÿฌ๋‚˜ ํŠธ๋žœ์ง€์Šคํ„ฐ์™€ ์ธํ„ฐ์ปค๋„ฅํŠธ์˜ ๋ณ€์ด๊ฐ€ ์ฆ๊ฐ€ํ•˜๊ณ  ์žˆ๊ณ  ๋””์ž์ธ ๋ฃฐ ์—ญ์‹œ ๋ณต์žกํ•ด์ง€๊ณ  ์žˆ๊ธฐ ๋•Œ๋ฌธ์— ํƒ€์ด๋ฐ ๋ถ„์„ ๋ฐ ๋””์ž์ธ ๋ฃฐ ์œ„๋ฐ˜ ์ œ๊ฑฐ๋Š” ์ดˆ๋ฏธ์„ธ ํšŒ๋กœ์—์„œ ๋” ์–ด๋ ค์›Œ์ง€๊ณ  ์žˆ๋‹ค. ๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ์ดˆ๋ฏธ์„ธ ์„ค๊ณ„๋ฅผ ์œ„ํ•œ ๋‘๊ฐ€์ง€ ๋ฌธ์ œ์ธ ํƒ€์ด๋ฐ ๋ถ„์„๊ณผ ๋””์ž์ธ ๋ฃฐ ์œ„๋ฐ˜์— ๋Œ€ํ•ด ๋‹ค๋ฃฌ๋‹ค. ์ฒซ๋ฒˆ์งธ๋กœ ๊ณต์ • ์ฝ”๋„ˆ์—์„œ ํƒ€์ด๋ฐ ๋ถ„์„์€ ์‹ค๋ฆฌ์ฝ˜์œผ๋กœ ์ œ์ž‘๋œ ํšŒ๋กœ์˜ ์„ฑ๋Šฅ์„ ์ •ํ™•ํžˆ ์˜ˆ์ธกํ•˜์ง€ ๋ชปํ•œ๋‹ค. ๊ทธ ์ด์œ ๋Š” ๊ณต์ • ์ฝ”๋„ˆ์—์„œ ๊ฐ€์žฅ ๋Š๋ฆฐ ํƒ€์ด๋ฐ ๊ฒฝ๋กœ๊ฐ€ ๋ชจ๋“  ๊ณต์ • ์กฐ๊ฑด์—์„œ๋„ ๊ฐ€์žฅ ๋Š๋ฆฐ ๊ฒƒ์€ ์•„๋‹ˆ๊ธฐ ๋•Œ๋ฌธ์ด๋‹ค. ๊ฒŒ๋‹ค๊ฐ€ ์นฉ ๋‚ด์˜ ์ž„๊ณ„ ๊ฒฝ๋กœ์—์„œ ์ธํ„ฐ์ปค๋„ฅํŠธ์— ์˜ํ•œ ์ง€์—ฐ ์‹œ๊ฐ„์ด ์ „์ฒด ์ง€์—ฐ ์‹œ๊ฐ„์—์„œ์˜ ์˜ํ–ฅ์ด ์ฆ๊ฐ€ํ•˜๊ณ  ์žˆ๊ณ , 10๋‚˜๋…ธ ์ดํ•˜ ๊ณต์ •์—์„œ๋Š” 20%๋ฅผ ์ดˆ๊ณผํ•˜๊ณ  ์žˆ๋‹ค. ์ฆ‰, ์‹ค๋ฆฌ์ฝ˜์œผ๋กœ ์ œ์ž‘๋œ ํšŒ๋กœ์˜ ์„ฑ๋Šฅ์„ ์ •ํ™•ํžˆ ์˜ˆ์ธกํ•˜๊ธฐ ์œ„ํ•ด์„œ๋Š” ๋Œ€ํ‘œ ํšŒ๋กœ๊ฐ€ ํŠธ๋žœ์ง€์Šคํ„ฐ์˜ ๋ณ€์ด ๋ฟ๋งŒ์•„๋‹ˆ๋ผ ์ธํ„ฐ์ปค๋„ฅํŠธ์˜ ๋ณ€์ด๋„ ๋ฐ˜์˜ํ•ด์•ผํ•œ๋‹ค. ์ธํ„ฐ์ปค๋„ฅํŠธ๋ฅผ ๊ตฌ์„ฑํ•˜๋Š” ๊ธˆ์†์ด 10์ธต ์ด์ƒ ์‚ฌ์šฉ๋˜๊ณ  ์žˆ๊ณ , ๊ฐ ์ธต์„ ๊ตฌ์„ฑํ•˜๋Š” ๊ธˆ์†์˜ ์ €ํ•ญ๊ณผ ์บํŒจ์‹œํ„ด์Šค์™€ ๋น„์•„ ์ €ํ•ญ์ด ๋ชจ๋‘ ํšŒ๋กœ ์ง€์—ฐ ์‹œ๊ฐ„์— ์˜ํ–ฅ์„ ์ฃผ๊ธฐ ๋•Œ๋ฌธ์— ๋Œ€ํ‘œ ํšŒ๋กœ๋ฅผ ์ฐพ๋Š” ๋ฌธ์ œ๋Š” ์ฐจ์›์ด ๋งค์šฐ ๋†’์€ ์˜์—ญ์—์„œ ์ตœ์ ์˜ ํ•ด๋ฅผ ์ฐพ๋Š” ๋ฐฉ๋ฒ•์ด ํ•„์š”ํ•˜๋‹ค. ์ด๋ฅผ ์œ„ํ•ด ์ธํ„ฐ์ปค๋„ฅํŠธ๋ฅผ ์ œ์ž‘ํ•˜๋Š” ๊ณต์ •(๋ฐฑ ์—”๋“œ ์˜ค๋ธŒ ๋ผ์ธ)์˜ ๋ณ€์ด๋ฅผ ๋ฐ˜์˜ํ•œ ๋Œ€ํ‘œ ํšŒ๋กœ๋ฅผ ์ƒ์„ฑํ•˜๋Š” ๋ฐฉ๋ฒ•์„ ์ œ์•ˆํ•˜์˜€๋‹ค. ๊ณต์ • ๋ณ€์ด๊ฐ€ ์—†์„๋•Œ ๊ฐ€์žฅ ๋Š๋ฆฐ ํƒ€์ด๋ฐ ๊ฒฝ๋กœ์— ์‚ฌ์šฉ๋œ ๊ฒŒ์ดํŠธ์™€ ๋ผ์šฐํŒ… ํŒจํ„ด์„ ๋ณ€๊ฒฝํ•˜๋ฉด์„œ ์ ์ง„์ ์œผ๋กœ ํƒ์ƒ‰ํ•˜๋Š” ๋ฐฉ๋ฒ•์ด๋‹ค. ๊ตฌ์ฒด์ ์œผ๋กœ, ๋ณธ ๋…ผ๋ฌธ์—์„œ ์ œ์•ˆํ•˜๋Š” ํ•ฉ์„ฑ ํ”„๋ ˆ์ž„์›Œํฌ๋Š” ๋‹ค์Œ์˜ ์ƒˆ๋กœ์šด ๊ธฐ์ˆ ๋“ค์„ ํ†ตํ•ฉํ•˜์˜€๋‹ค: (1) ๋ผ์šฐํŒ…์„ ๊ตฌ์„ฑํ•˜๋Š” ์—ฌ๋Ÿฌ ๊ธˆ์† ์ธต๊ณผ ๋น„์•„๋ฅผ ์ถ”์ถœํ•˜๊ณ  ํƒ์ƒ‰ ์‹œ๊ฐ„ ๊ฐ์†Œ๋ฅผ ์œ„ํ•ด ์œ ์‚ฌํ•œ ๊ตฌ์„ฑ๋“ค์„ ๊ฐ™์€ ๋ฒ”์ฃผ๋กœ ๋ถ„๋ฅ˜ํ•˜์˜€๋‹ค. (2) ๋น ๋ฅด๊ณ  ์ •ํ™•ํ•œ ํƒ€์ด๋ฐ ๋ถ„์„์„ ์œ„ํ•˜์—ฌ ์—ฌ๋Ÿฌ ๊ธˆ์† ์ธต๊ณผ ๋น„์•„๋“ค์˜ ๋ณ€์ด๋ฅผ ์ˆ˜์‹ํ™”ํ•˜์˜€๋‹ค. (3) ํ™•์žฅ์„ฑ์„ ๊ณ ๋ คํ•˜์—ฌ ์ผ๋ฐ˜์ ์ธ ๋ง ์˜ค์‹ค๋ ˆ์ดํ„ฐ๋กœ ๋Œ€ํ‘œํšŒ๋กœ๋ฅผ ํƒ์ƒ‰ํ•˜์˜€๋‹ค. ๋‘๋ฒˆ์งธ๋กœ ๋””์ž์ธ ๋ฃฐ์˜ ๋ณต์žก๋„๊ฐ€ ์ฆ๊ฐ€ํ•˜๊ณ  ์žˆ๊ณ , ์ด๋กœ ์ธํ•ด ํ‘œ์ค€ ์…€๋“ค์˜ ์ธํ„ฐ์ปค๋„ฅํŠธ๋ฅผ ํ†ตํ•œ ์—ฐ๊ฒฐ์„ ์ง„ํ–‰ํ•˜๋Š” ๋™์•ˆ ๋””์ž์ธ ๋ฃฐ ์œ„๋ฐ˜์ด ์ฆ๊ฐ€ํ•˜๊ณ  ์žˆ๋‹ค. ๊ฒŒ๋‹ค๊ฐ€ ํ‘œ์ค€ ์…€์˜ ํฌ๊ธฐ๊ฐ€ ๊ณ„์† ์ž‘์•„์ง€๋ฉด์„œ ์…€๋“ค์˜ ์—ฐ๊ฒฐ์€ ์ ์  ์–ด๋ ค์›Œ์ง€๊ณ  ์žˆ๋‹ค. ๊ธฐ์กด์—๋Š” ํšŒ๋กœ ๋‚ด ๋ชจ๋“  ํ‘œ์ค€ ์…€์„ ์—ฐ๊ฒฐํ•˜๋Š”๋ฐ ํ•„์š”ํ•œ ํŠธ๋ž™ ์ˆ˜, ๊ฐ€๋Šฅํ•œ ํŠธ๋ž™ ์ˆ˜, ์ด๋“ค ๊ฐ„์˜ ์ฐจ์ด๋ฅผ ์ด์šฉํ•˜์—ฌ ์—ฐ๊ฒฐ ๊ฐ€๋Šฅ์„ฑ์„ ํŒ๋‹จํ•˜๊ณ , ๋””์ž์ธ ๋ฃฐ ์œ„๋ฐ˜์ด ๋ฐœ์ƒํ•˜์ง€ ์•Š๋„๋ก ์…€ ๋ฐฐ์น˜๋ฅผ ์ตœ์ ํ™”ํ•˜์˜€๋‹ค. ๊ทธ๋Ÿฌ๋‚˜ ๊ธฐ์กด ๋ฐฉ๋ฒ•์€ ์ตœ์‹  ๊ณต์ •์—์„œ๋Š” ์ •ํ™•ํ•˜์ง€ ์•Š๊ธฐ ๋•Œ๋ฌธ์— ๋” ๋งŽ์€ ์ •๋ณด๋ฅผ ์ด์šฉํ•œ ํšŒ๋กœ๋‚ด ๋ชจ๋“  ํ‘œ์ค€ ์…€ ์‚ฌ์ด์˜ ์—ฐ๊ฒฐ ๊ฐ€๋Šฅ์„ฑ์„ ์˜ˆ์ธกํ•˜๋Š” ๋ฐฉ๋ฒ•์ด ํ•„์š”ํ•˜๋‹ค. ๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ๊ธฐ๊ณ„ ํ•™์Šต์„ ํ†ตํ•ด ๋””์ž์ธ ๋ฃฐ ์œ„๋ฐ˜์ด ๋ฐœ์ƒํ•˜๋Š” ์˜์—ญ ๋ฐ ๊ฐœ์ˆ˜๋ฅผ ์˜ˆ์ธกํ•˜๊ณ  ์ด๋ฅผ ์ค„์ด๊ธฐ ์œ„ํ•ด ํ‘œ์ค€ ์…€์˜ ๋ฐฐ์น˜๋ฅผ ๋ฐ”๊พธ๋Š” ๋ฐฉ๋ฒ•์„ ์ œ์•ˆํ•˜์˜€๋‹ค. ๋””์ž์ธ ๋ฃฐ ์œ„๋ฐ˜ ์˜์—ญ์€ ์ด์ง„ ๋ถ„๋ฅ˜๋กœ ์˜ˆ์ธกํ•˜์˜€๊ณ  ํ‘œ์ค€ ์…€์˜ ๋ฐฐ์น˜๋Š” ๋””์ž์ธ ๋ฃฐ ์œ„๋ฐ˜ ๊ฐœ์ˆ˜๋ฅผ ์ตœ์†Œํ™”ํ•˜๋Š” ๋ฐฉํ–ฅ์œผ๋กœ ์ตœ์ ํ™”๋ฅผ ์ˆ˜ํ–‰ํ•˜์˜€๋‹ค. ์ œ์•ˆํ•˜๋Š” ํ”„๋ ˆ์ž„์›Œํฌ๋Š” ๋‹ค์Œ์˜ ์„ธ๊ฐ€์ง€ ๊ธฐ์ˆ ๋กœ ๊ตฌ์„ฑ๋˜์—ˆ๋‹ค: (1) ํšŒ๋กœ ๋ ˆ์ด์•„์›ƒ์„ ์—ฌ๋Ÿฌ ๊ฐœ์˜ ์ •์‚ฌ๊ฐํ˜• ๊ฒฉ์ž๋กœ ๋‚˜๋ˆ„๊ณ  ๊ฐ ๊ฒฉ์ž์—์„œ ๋ผ์šฐํŒ…์„ ์˜ˆ์ธกํ•  ์ˆ˜ ์žˆ๋Š” ์š”์†Œ๋“ค์„ ์ถ”์ถœํ•œ๋‹ค. (2) ๊ฐ ๊ฒฉ์ž์—์„œ ๋””์ž์ธ ๋ฃฐ ์œ„๋ฐ˜์ด ์žˆ๋Š”์ง€ ์—ฌ๋ถ€๋ฅผ ํŒ๋‹จํ•˜๋Š” ์ด์ง„ ๋ถ„๋ฅ˜๋ฅผ ์ˆ˜ํ–‰ํ•œ๋‹ค. (3) ๋ฉ”ํƒ€ํœด๋ฆฌ์Šคํ‹ฑ ์ตœ์ ํ™” ๋˜๋Š” ๋ฒ ์ด์ง€์•ˆ ์ตœ์ ํ™”๋ฅผ ์ด์šฉํ•˜์—ฌ ์ „์ฒด ๋””์ž์ธ ๋ฃฐ ์œ„๋ฐ˜ ๊ฐœ์ˆ˜๊ฐ€ ๊ฐ์†Œํ•˜๋„๋ก ๊ฐ ๊ฒฉ์ž์— ์žˆ๋Š” ํ‘œ์ค€ ์…€์„ ์›€์ง์ธ๋‹ค.Timing analysis and clearing design rule violations are the essential steps for taping out a chip. However, they keep getting harder in deep sub-micron circuits because the variations of transistors and interconnects have been increasing and design rules have become more complex. This dissertation addresses two problems on timing analysis and design rule violations for synthesizing deep sub-micron circuits. Firstly, timing analysis in process corners can not capture post-Si performance accurately because the slowest path in the process corner is not always the slowest one in the post-Si instances. In addition, the proportion of interconnect delay in the critical path on a chip is increasing and becomes over 20% in sub-10nm technologies, which means in order to capture post-Si performance accurately, the representative critical path circuit should reflect not only FEOL (front-end-of-line) but also BEOL (backend-of-line) variations. Since the number of BEOL metal layers exceeds ten and the layers have variation on resistance and capacitance intermixed with resistance variation on vias between them, a very high dimensional design space exploration is necessary to synthesize a representative critical path circuit which is able to provide an accurate performance prediction. To cope with this, I propose a BEOL-aware methodology of synthesizing a representative critical path circuit, which is able to incrementally explore, starting from an initial path circuit on the post-Si target circuit, routing patterns (i.e., BEOL reconfiguring) as well as gate resizing on the path circuit. Precisely, the synthesis framework of critical path circuit integrates a set of novel techniques: (1) extracting and classifying BEOL configurations for lightening design space complexity, (2) formulating BEOL random variables for fast and accurate timing analysis, and (3) exploring alternative (ring oscillator) circuit structures for extending the applicability of this work. Secondly, the complexity of design rules has been increasing and results in more design rule violations during routing. In addition, the size of standard cell keeps decreasing and it makes routing harder. In the conventional P&R flow, the routability of pre-routed layout is predicted by routing congestion obtained from global routing, and then placement is optimized not to cause design rule violations. But it turned out to be inaccurate in advanced technology nodes so that it is necessary to predict routability with more features. I propose a methodology of predicting the hotspots of design rule violations (DRVs) using machine learning with placement related features and the conventional routing congestion, and perturbating placed cells to reduce the number of DRVs. Precisely, the hotspots are predicted by a pre-trained binary classification model and placement perturbation is performed by global optimization methods to minimize the number of DRVs predicted by a pre-trained regression model. To do this, the framework is composed of three techniques: (1) dividing the circuit layout into multiple rectangular grids and extracting features such as pin density, cell density, global routing results (demand, capacity and overflow), and more in the placement phase, (2) predicting if each grid has DRVs using a binary classification model, and (3) perturbating the placed standard cells in the hotspots to minimize the number of DRVs predicted by a regression model.1 Introduction 1 1.1 Representative Critical Path Circuit . . . . . . . . . . . . . . . . . . . 1 1.2 Prediction of Design Rule Violations and Placement Perturbation . . . 5 1.3 Contributions of This Dissertation . . . . . . . . . . . . . . . . . . . 7 2 Methodology for Synthesizing Representative Critical Path Circuits reflecting BEOL Timing Variation 9 2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Definitions and Overall Flow . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Techniques for BEOL-Aware RCP Generation . . . . . . . . . . . . . 17 2.3.1 Clustering BEOL Configurations . . . . . . . . . . . . . . . . 17 2.3.2 Formulating Statistical BEOL Random Variables . . . . . . . 18 2.3.3 Delay Modeling . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.4 Exploring Ring Oscillator Circuit Structures . . . . . . . . . . 24 2.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.5 Further Study on Variations . . . . . . . . . . . . . . . . . . . . . . . 37 3 Methodology for Reducing Routing Failures through Enhanced Prediction on Design Rule Violations in Placement 39 3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3 Techniques for Reducing Routing Failures . . . . . . . . . . . . . . . 43 3.3.1 Binary Classification . . . . . . . . . . . . . . . . . . . . . . 43 3.3.2 Regression . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.3 Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.4 Placement Perturbation . . . . . . . . . . . . . . . . . . . . . 47 3.4 Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.4.1 Experiments Setup . . . . . . . . . . . . . . . . . . . . . . . 51 3.4.2 Hotspot Prediction . . . . . . . . . . . . . . . . . . . . . . . 51 3.4.3 Regression . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.4.4 Placement Perturbation . . . . . . . . . . . . . . . . . . . . . 57 4 Conclusions 61 4.1 Synthesis of Representative Critical Path Circuits reflecting BEOL Timing Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.2 Reduction of Routing Failures through Enhanced Prediction on Design Rule Violations in Placement . . . . . . . . . . . . . . . . . . . . . . 62 Abstract (In Korean) 69Docto

    A Survey of Prediction and Classification Techniques in Multicore Processor Systems

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    In multicore processor systems, being able to accurately predict the future provides new optimization opportunities, which otherwise could not be exploited. For example, an oracle able to predict a certain application\u27s behavior running on a smart phone could direct the power manager to switch to appropriate dynamic voltage and frequency scaling modes that would guarantee minimum levels of desired performance while saving energy consumption and thereby prolonging battery life. Using predictions enables systems to become proactive rather than continue to operate in a reactive manner. This prediction-based proactive approach has become increasingly popular in the design and optimization of integrated circuits and of multicore processor systems. Prediction transforms from simple forecasting to sophisticated machine learning based prediction and classification that learns from existing data, employs data mining, and predicts future behavior. This can be exploited by novel optimization techniques that can span across all layers of the computing stack. In this survey paper, we present a discussion of the most popular techniques on prediction and classification in the general context of computing systems with emphasis on multicore processors. The paper is far from comprehensive, but, it will help the reader interested in employing prediction in optimization of multicore processor systems

    AI/ML Algorithms and Applications in VLSI Design and Technology

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    An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

    Reliable Design of Three-Dimensional Integrated Circuits

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    ๋ฌผ๋ฆฌ์  ์„ค๊ณ„ ์ž๋™ํ™”์—์„œ ํ‘œ์ค€์…€ ํ•ฉ์„ฑ ๋ฐ ์ตœ์ ํ™”์™€ ์„ค๊ณ„ ํ’ˆ์งˆ ์˜ˆ์ธก ๋ฐฉ๋ฒ•๋ก 

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    ํ•™์œ„๋…ผ๋ฌธ(๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2023. 2. ๊น€ํƒœํ™˜.In the physical design of chip implementation, designing high-quality standard cell layout and accurately predicting post-route DRV (design rule violation) at an early stage is an important problem, especially in advanced technology nodes. This dissertation presents two methodologies that can contribute to improving the design quality and design turnaround time of physical design flow. Firstly, we propose an integrated approach to the two problems of transistor folding and placement in standard cell layout synthesis. Precisely, we propose a globally optimal algorithm of search tree based design space exploration, devising a set of effective speeding up techniques as well as dynamic programming based fast cost computation. In addition, our algorithm incorporates the minimum oxide diffusion jog constraint, which closely relies on both of transistor folding and placement. Through experiments with the transistor netlists and design rules in advanced node, our proposed method is able to synthesize fully routable cell layouts of minimal size within a very fast time for each netlist, outperforming the cell layout quality in the manual design. Secondly, we propose a novel ML based DRC hotspot prediction technique, which is able to accurately capture the combined impact of pin accessibility and routing congestion on DRC hotspots. Precisely, we devise a graph, called pin proximity graph, that effectively models the spatial information on cell I/O pins and the information on pin-to-pin disturbance relation. Then, we propose a new ML model, which tightly combines GNN (graph neural network) and U-net in a way that GNN is used to embed pin accessibility information abstracted from our pin proximity graph while U-net is used to extract routing congestion information from grid-based features. Through experiments with a set of benchmark designs using advanced node, our model outperforms the existing ML models on all benchmark designs within the fast inference time in comparison with that of the state-of-the-art techniques.์นฉ ๊ตฌํ˜„์˜ ๋ฌผ๋ฆฌ์  ์„ค๊ณ„ ๋‹จ๊ณ„์—์„œ, ๋†’์€ ์„ฑ๋Šฅ์˜ ํ‘œ์ค€ ์…€ ์„ค๊ณ„์™€ ๋ฐฐ์„  ์—ฐ๊ฒฐ ์ดํ›„ ์กฐ๊ธฐ์— ์„ค๊ณ„ ๊ทœ์น™ ์œ„๋ฐ˜์„ ์ •ํ™•ํžˆ ์˜ˆ์ธกํ•˜๋Š” ๊ฒƒ์€ ์ตœ์‹  ๊ณต์ •์—์„œ ํŠนํžˆ ์ค‘์š”ํ•œ ๋ฌธ์ œ์ด๋‹ค. ๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ๋ฌผ๋ฆฌ์  ์„ค๊ณ„์—์„œ์˜ ์„ค๊ณ„ ํ’ˆ์งˆ๊ณผ ์ด ์„ค๊ณ„ ์‹œ๊ฐ„ ํ–ฅ์ƒ์„ ๋‹ฌ์„ฑํ•  ์ˆ˜ ์žˆ๋Š” ๋‘ ๊ฐ€์ง€ ๋ฐฉ๋ฒ•๋ก ์„ ์ œ์•ˆํ•œ๋‹ค. ๋จผ์ €, ๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ํ‘œ์ค€ ์…€ ๋ ˆ์ด์•„์›ƒ ํ•ฉ์„ฑ์—์„œ ํŠธ๋žœ์ง€์Šคํ„ฐ ํด๋”ฉ๊ณผ ๋ฐฐ์น˜๋ฅผ ์ข…ํ•ฉ์ ์œผ๋กœ ์ง„ํ–‰ํ•  ์ˆ˜ ์žˆ๋Š” ๋ฐฉ๋ฒ•๋ก ์„ ๋…ผํ•œ๋‹ค. ๊ตฌ์ฒด์ ์œผ๋กœ ํƒ์ƒ‰ ํŠธ๋ฆฌ ๊ธฐ๋ฐ˜์˜ ์ตœ์ ํ™” ์•Œ๊ณ ๋ฆฌ์ฆ˜๊ณผ ๋™์  ํ”„๋กœ๊ทธ๋ž˜๋ฐ ๊ธฐ๋ฐ˜ ๋น ๋ฅธ ๋น„์šฉ ๊ณ„์‚ฐ ๋ฐฉ๋ฒ•๊ณผ ์—ฌ๋Ÿฌ ์†๋„ ๊ฐœ์„  ๊ธฐ๋ฒ•์„ ์ œ์•ˆํ•œ๋‹ค. ์—ฌ๊ธฐ์— ๋”ํ•ด, ์ตœ์‹  ๊ณต์ •์—์„œ ํŠธ๋žœ์ง€์Šคํ„ฐ ํด๋”ฉ๊ณผ ๋ฐฐ์น˜๋กœ ์ธํ•ด ๋ฐœ์ƒํ•  ์ˆ˜ ์žˆ๋Š” ์ตœ์†Œ ์‚ฐํ™”๋ฌผ ํ™•์‚ฐ ์˜์—ญ ์„ค๊ณ„ ๊ทœ์น™์„ ๊ณ ๋ คํ•˜์˜€๋‹ค. ์ตœ์‹  ๊ณต์ •์— ๋Œ€ํ•œ ํ‘œ์ค€ ์…€ ํ•ฉ์„ฑ ์‹คํ—˜ ๊ฒฐ๊ณผ, ๋ณธ ๋…ผ๋ฌธ์—์„œ ์ œ์•ˆํ•œ ๋ฐฉ๋ฒ•์ด ์„ค๊ณ„ ์ „๋ฌธ๊ฐ€๊ฐ€ ์ˆ˜๋™์œผ๋กœ ์„ค๊ณ„ํ•œ ๊ฒƒ ๋Œ€๋น„ ๋†’์€ ์„ฑ๋Šฅ์„ ๋ณด์ด๊ณ , ์„ค๊ณ„ ์‹œ๊ฐ„๋„ ๋งค์šฐ ์งง์Œ์„ ๋ณด์ธ๋‹ค. ๋‘๋ฒˆ์งธ๋กœ, ๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ์…€ ๋ฐฐ์น˜ ๋‹จ๊ณ„์—์„œ ํ•€ ์ ‘๊ทผ์„ฑ๊ณผ ์—ฐ๊ฒฐ ํ˜ผ์žก์œผ๋กœ ์ธํ•œ ์˜ํ–ฅ์„ ์ข…ํ•ฉ์ ์œผ๋กœ ๊ณ ๋ คํ•  ์ˆ˜ ์žˆ๋Š” ๋จธ์‹  ๋Ÿฌ๋‹ ๊ธฐ๋ฐ˜ ์„ค๊ณ„ ๊ทœ์น™ ์œ„๋ฐ˜ ๊ตฌ์—ญ ์˜ˆ์ธก ๋ฐฉ๋ฒ•๋ก ์„ ์ œ์•ˆํ•œ๋‹ค. ๋จผ์ € ํ‘œ์ค€ ์…€์˜ ์ž…/์ถœ๋ ฅ ํ•€์˜ ๋ฌผ๋ฆฌ์  ์ •๋ณด์™€ ํ•€๊ณผ ํ•€ ์‚ฌ์ด ๋ฐฉํ•ด ๊ด€๊ณ„๋ฅผ ํšจ๊ณผ์ ์œผ๋กœ ํ‘œํ˜„ํ•  ์ˆ˜ ์žˆ๋Š” ํ•€ ๊ทผ์ ‘ ๊ทธ๋ž˜ํ”„๋ฅผ ์ œ์•ˆํ•˜๊ณ , ๊ทธ๋ž˜ํ”„ ์‹ ๊ฒฝ๋ง๊ณผ ์œ ๋„ท ์‹ ๊ฒฝ๋ง์„ ํšจ๊ณผ์ ์œผ๋กœ ๊ฒฐํ•ฉํ•œ ์ƒˆ๋กœ์šด ํ˜•ํƒœ์˜ ๋จธ์‹  ๋Ÿฌ๋‹ ๋ชจ๋ธ์„ ์ œ์•ˆํ•œ๋‹ค. ์ด ๋ชจ๋ธ์—์„œ ๊ทธ๋ž˜ํ”„ ์‹ ๊ฒฝ๋ง์€ ํ•€ ๊ทผ์ ‘ ๊ทธ๋ž˜ํ”„๋กœ๋ถ€ํ„ฐ ํ•€ ์ ‘๊ทผ์„ฑ ์ •๋ณด๋ฅผ ์ถ”์ถœํ•˜๊ณ , ์œ ๋„ท ์‹ ๊ฒฝ๋ง์€ ๊ฒฉ์ž ๊ธฐ๋ฐ˜ ํŠน์ง•์œผ๋กœ๋ถ€ํ„ฐ ์—ฐ๊ฒฐ ํ˜ผ์žก ์ •๋ณด๋ฅผ ์ถ”์ถœํ•œ๋‹ค. ์‹คํ—˜ ๊ฒฐ๊ณผ ๋ณธ ๋…ผ๋ฌธ์—์„œ ์ œ์•ˆํ•œ ๋ฐฉ๋ฒ•์€ ์ด์ „ ์—ฐ๊ตฌ๋“ค ๋Œ€๋น„ ๋” ๋น ๋ฅธ ์˜ˆ์ธก ์‹œ๊ฐ„์— ๋” ๋†’์€ ์˜ˆ์ธก ์„ฑ๋Šฅ์„ ๋‹ฌ์„ฑํ•จ์„ ๋ณด์ธ๋‹ค.1 Introduction 1 1.1 Standard Cell Layout Synthesis 1 1.2 Machine Learning for Electronic Design Automation 6 1.3 Prediction of Design Rule Violation 8 1.4 Contributions of This Dissertation 11 2 Standard Cell Layout Synthesis of Advanced Nodes with Simultaneous Transistor Folding and Placement 14 2.1 Motivations 14 2.2 Algorithm for Standard Cell Layout Synthesis 16 2.2.1 Problem Definition 16 2.2.2 Overall Flow 18 2.2.3 Step 1: Generation of Folding Shapes 18 2.2.4 Step 2: Search-tree Based Design Space Exploration 20 2.2.5 Speeding up Techniques 23 2.2.6 In-cell Routability Estimation 28 2.2.7 Step 3: In-cell Routing 30 2.2.8 Step 4: Splitting Folding Shapes 35 2.2.9 Step 5: Relaxing Minimum-area Constraints 37 2.3 Experimental Results 38 2.3.1 Comparison with ASAP 7nm Cell Layouts 40 2.3.2 Effectiveness of Dynamic Folding 42 2.3.3 Effectiveness of Speeding Up Techniques 43 2.3.4 Impact of Splitting Folding Shape 48 2.3.5 Runtime Analysis According to Area Relaxation 51 2.3.6 Comparison with Previous Works 52 3 Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction using Graph Neural Network and U-Net 54 3.1 Preliminary 54 3.1.1 Graph Neural Network 54 3.1.2 Fully Convolutional Network 56 3.2 Proposed Prediction Methodology 57 3.2.1 Overall Flow 57 3.2.2 Pin Proximity Graph 58 3.2.3 Grid-based Features 61 3.2.4 Overall Architecture of PGNN 64 3.2.5 GNN Architecture in PGNN 64 3.2.6 U-net Architecture in PGNN 66 3.2.7 Final Prediction in PGNN 66 3.3 Experimental Results 68 3.3.1 Experimental Setup 68 3.3.2 Analysis on PGNN Performance 71 3.3.3 Comparison with Previous Works 72 3.3.4 Adaptation to Real-world Designs 81 3.3.5 Handling Data Imbalance Problem in Regression Model 86 4 Conclusions 92 4.1 Chapter 2 92 4.2 Chapter 3 93๋ฐ•

    Towards Machine Learning-Based FPGA Backend Flow: Challenges and Opportunities

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    Field-Programmable Gate Array (FPGA) is at the core of System on Chip (SoC) design across various Industry 5.0 digital systemsโ€”healthcare devices, farming equipment, autonomous vehicles and aerospace gear to name a few. Given that pre-silicon verification using Computer Aided Design (CAD) accounts for about 70% of the time and money spent on the design of modern digital systems, this paper summarizes the machine learning (ML)-oriented efforts in different FPGA CAD design steps. With the recent breakthrough of machine learning, FPGA CAD tasksโ€”high-level synthesis (HLS), logic synthesis, placement and routingโ€”are seeing a renewed interest in their respective decision-making steps. We focus on machine learning-based CAD tasks to suggest some pertinent research areas requiring more focus in CAD design. The development of open-source benchmarks optimized for an end-to-end machine learning experience, intra-FPGA optimization, domain-specific accelerators, lack of explainability and federated learning are the issues reviewed to identify important research spots requiring significant focus. The potential of the new cloud-based architectures to understand the application of the right ML algorithms in FPGA CAD decision-making steps is discussed, together with visualizing the scenario of incorporating more intelligence in the cloud platform, with the help of relatively newer technologies such as CAD as Adaptive OpenPlatform Service (CAOS). Altogether, this research explores several research opportunities linked with modern FPGA CAD flow design, which will serve as a single point of reference for modern FPGA CAD flow design

    Algorithmic techniques for physical design : macro placement and under-the-cell routing

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    With the increase of chip component density and new manufacturability constraints imposed by modern technology nodes, the role of algorithms for electronic design automation is key to the successful implementation of integrated circuits. Two of the critical steps in the physical design flows are macro placement and ensuring all design rules are honored after timing closure. This thesis proposes contributions to help in these stages, easing time-consuming manual steps and helping physical design engineers to obtain better layouts in reduced turnaround time. The first contribution is under-the-cell routing, a proposal to systematically connect standard cell components via lateral pins in the lower metal layers. The aim is to reduce congestion in the upper metal layers caused by extra metal and vias, decreasing the number of design rule violations. To allow cells to connect by abutment, a standard cell library is enriched with instances containing lateral pins in a pre-selected sharing track. Algorithms are proposed to maximize the numbers of connections via lateral connection by mapping placed cell instances to layouts with lateral pins, and proposing local placement modifications to increase the opportunities for such connections. Experimental results show a significant decrease in the number of pins, vias, and in number of design rule violations, with negligible impact on wirelength and timing. The second contribution, done in collaboration with eSilicon (a leading ASIC design company), is the creation of HiDaP, a macro placement tool for modern industrial designs. The proposed approach follows a multilevel scheme to floorplan hierarchical blocks, composed of macros and standard cells. By exploiting RTL information available in the netlist, the dataflow affinity between these blocks is modeled and minimized to find a macro placement with good wirelength and timing properties. The approach is further extended to allow additional engineer input, such as preferred macro locations, and also spectral and force methods to guide the floorplanning search. Experimental results show that the layouts generated by HiDaP outperforms those obtained by a state-of-the-art EDA physical design software, with similar wirelength and better timing when compared to manually designed tape-out ready macro placements. Layouts obtained by HiDaP have successfully been brought to near timing closure with one to two rounds of small modifications by physical design engineers. HiDaP has been fully integrated in the design flows of the company and its development remains an ongoing effort.A causa de l'increment de la densitat de components en els xip i les noves restriccions de disseny imposades pels รบltims nodes de fabricaciรณ, el rol de l'algorรญsmia en l'automatitzaciรณ del disseny electrรฒnic ha esdevingut clau per poder implementar circuits integrats. Dos dels passos crucials en el procรฉs de disseny fรญsic รฉs el placement de macros i assegurar la correcciรณ de les regles de disseny un cop les restriccions de timing del circuit sรณn satisfetes. Aquesta tesi proposa contribucions per ajudar en aquests dos reptes, facilitant laboriosos passos manuals en el procรฉs i ajudant als enginyers de disseny fรญsic a obtenir millors resultats en menys temps. La primera contribuciรณ รฉs el routing "under-the-cell", una proposta per connectar celยทles estร ndard usant pins laterals en les capes de metall inferior de manera sistemร tica. L'objectiu รฉs reduir la congestiรณ en les capes de metall superior causades per l'รบs de metall i vies, i aixรญ disminuir el nombre de violacions de regles de disseny. Per permetre la connexiรณ lateral de celยทles, estenem una llibreria de celยทles estร ndard amb dissenys que incorporen connexions laterals. Tambรฉ proposem modificacions locals al placement per permetre explotar aquest tipus de connexions mรฉs sovint. Els resultats experimentals mostren una reducciรณ significativa en el nombre de pins, vies i nombre de violacions de regles de disseny, amb un impacte negligible en wirelength i timing. La segona contribuciรณ, desenvolupada en colยทlaboraciรณ amb eSilicon (una empresa capdavantera en disseny ASIC), รฉs el desenvolupament de HiDaP, una eina de macro placement per a dissenys industrials actuals. La proposta segueix un procรฉs multinivell per fer el floorplan de blocks jerร rquics, formats per macros i celยทles estร ndard. Mitjanรงant la informaciรณ RTL disponible en la netlist, l'afinitat de dataflow entre els mรฒduls es modela i minimitza per trobar macro placements amb bones propietats de wirelength i timing. La proposta tambรฉ incorpora la possibilitat de rebre input addicional de l'enginyer, com ara suggeriments de les posicions de les macros. Finalment, tambรฉ usa mรจtodes espectrals i de forรงes per guiar la cerca de floorplans. Els resultats experimentals mostren que els dissenys generats amb HiDaP sรณn millors que els obtinguts per eines comercials capdavanteres de EDA. Els resultats tambรฉ mostren que els dissenys presentats poden obtenir un wirelength similar i millor timing que macro placements obtinguts manualment, usats per fabricaciรณ. Alguns dissenys obtinguts per HiDaP s'han dut fins a timing-closure en una o dues rondes de modificacions incrementals per part d'enginyers de disseny fรญsic. L'eina s'ha integrat en el procรฉs de disseny de eSilicon i el seu desenvolupament continua mรฉs enllร  de les aportacions a aquesta tesi
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