Perspective of buried oxide thickness variation on triple metal-gate (TMG) recessed-S/D FD-SOI MOSFET

Recently, Fully-Depleted Silicon on Insulator (FD-SOI) MOSFETs have been accepted as a favourable technology beyond nanometer nodes, and the technique of Recessed-Source/Drain (Re-S/D) has made it more immune in regards of various performance factors. However, the proper selection of Buried-Oxide (BOX) thickness is one of the major challenges in the design of FD-SOI based MOS devices in order to suppress the drain electric penetrations across the BOX interface efficiently. In this work, the effect of BOX thickness on the performance of TMG Re-S/D FD-SOI MOSFET has been presented at 60 nm gate length. The perspective of BOX thickness variation has been analysed on the basis of its surface potential profile and the extraction of the threshold voltage by performing two-dimensional numerical simulations. Moreover, to verify the short channel immunity, the impact of gate length scaling has also been discussed. It is found that the device attains two step-up potential profile with suppressed short channel effects. The outcomes reveal that the Drain Induced Barrier Lowering (DIBL) values are lower among conventional SOI MOSFETs. The device has been designed and simulated by using 2D numerical ATLAS Silvaco TCAD simulator

Modeling and Simulation of Subthreshold Characteristics of Short-Channel Fully-Depleted Recessed-Source/Drain SOI MOSFETs

Non-conventional metal-oxide-semiconductor (MOS) devices have attracted researchers‟ attention for future ultra-large-scale-integration (ULSI) applications since the channel length of conventional MOS devices approached the physical limit. Among the non-conventional CMOS devices which are currently being pursued for the future ULSI, the fully-depleted (FD) SOI MOSFET is a serious contender as the SOI MOSFETs possess some unique features such as enhanced short-channel effects immunity, low substrate leakage current, and compatibility with the planar CMOS technology. However, due to the ultra-thin source and drain regions, FD SOI MOSFETs possess large series resistance which leads to the poor current drive capability of the device despite having excellent short-channel characteristics. To overcome this large series resistance problem, the source/drain area may be increased by extending S/D either upward or downward. Hence, elevated-source/drain (E-S/D) and recessed-source/drain (Re-S/D) are the two structures which can be used to minimize the series resistance problem. Due to the undesirable issues such as parasitic capacitance, current crowding effects, etc. with E-S/D structure, the Re-S/D structure is a better choice. The FD Re-S/D SOI MOSFET may be an attractive option for sub-45nm regime because of its low parasitic capacitances, reduced series resistance, high drive current, very high switching speed and compatibility with the planar CMOS technology. The present dissertation is to deal with the theoretical modeling and computer-based simulation of the FD SOI MOSFETs in general, and recessed source/drain (Re-S/D) ultra-thin-body (UTB) SOI MOSFETs in particular. The current drive capability of Re-S/D UTB SOI MOSFETs can be further improved by adopting the dual-metal-gate (DMG) structure in place of the conventional single-metal-gate-structure. However, it will be interesting to see how the presence of two metals as gate contact changes the subthreshold characteristics of the device. Hence, the effects of adopting DMG structure on the threshold voltage, subthreshold swing and leakage current of Re-S/D UTB SOI MOSFETs have been studied in this dissertation. Further, high-k dielectric materials are used in ultra-scaled MOS devices in order to cut down the quantum mechanical tunneling of carriers. However, a physically thick gate dielectric causes fringing field induced performance degradation. Therefore, the impact of high-k dielectric materials on subthreshold characteristics of Re-S/D SOI MOSFETs needs to be investigated. In this dissertation, various subthreshold characteristics of the device with high-k gate dielectric and metal gate electrode have been investigated in detail. Moreover, considering the variability problem of threshold voltage in ultra-scaled devices, the presence of a back-gate bias voltage may be useful for ultimate tuning of the threshold voltage and other characteristics. Hence, the impact of back-gate bias on the important subthreshold characteristics such as threshold voltage, subthreshold swing and leakage currents of Re-S/D UTB SOI MOSFETs has been thoroughly analyzed in this dissertation. The validity of the analytical models are verified by comparing model results with the numerical simulation results obtained from ATLAS™, a device simulator from SILVACO Inc

Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET

In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate's threshold voltage (VTH1) could be reduced compared to the external gate (VTH2) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs)

Analytical Modeling of Channel Noise for Gate Material Engineered Surrounded/Cylindrical Gate (SGT/CGT) MOSFET

In this paper, an analytical modeling is presentated to describe the channel noise in GME SGT/CGT MOSFET, based on explicit functions of MOSFETs geometry and biasing conditions for all channel length down to deep submicron and is verified with the experimental data. Results shows the impact of various parameters such as gate bias, drain bias, channel length ,device diameter and gate material work function difference on drain current noise spectral density of the device reflecting its applicability for circuit design applications

SPICE model of drain induced barrier lowering in sub-10 nm junctionless cylindrical surrounding gate MOSFET

We propose a SPICE Drain Induced Barrier Lowering (DIBL) model for sub-10 nm Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs. The DIBL shows the proportionl relation to the -3 power of the channel length Lg and the 2 power of silicon thickness in MOSFET having a rectangular channel, but this relation cannot be used in cylindrical channel because of the difference in channel structure. The subthreshold currents, including the tunneling current from the WKB (Wentzel-Kramers-Brillouin) approximation as well as the diffusion-drift current, are used in the model. The constant current method is used to define the threshold voltage as the gate voltage at a constant current, (2πR/Lg)10-7 A for channel length and channel radius R. The central potential of the JLCSG MOSFET is determined by the Poisson equation. As a result, it can be seen that the DIBL of the JLCSG MOSFET is proportional to the –2.76 power of the channel length, to the 1.76 power of the channel radius, and linearly to the oxide film thickness. At this time, we observe that the SPICE parameter, the static feedback coefficient, has a value less than 1 1, and this model can be used to analyze the DIBL of the JLCSG MOSFET

Design and analytical performance of subthreshold characteristics of CSDG MOSFET.

Masters Degree. University of KwaZulu-Natal, Durban.The downscaling of the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) devices have been the driving force for Nanotechnology and Very Large-Scale Integration (VLSI) systems. This is affirmed by Moore’s law which states that “The number of transistors placed in an Integrated Circuit (IC) or chip doubles approximately every two years”. The main objectives for the transistor scaling are: to increase functionality, switching speed, packing density and lower the operating power of the ICs. However, the downscaling of the MOSFET device is posed with various challenges such as the threshold roll-off, Drain Induced Barrier Lowing (DIBL), surface scattering, and velocity saturation known as Short Channel Effects (SCEs). To overcome these challenges, a cylindrically structured MOSFET is employed because it increases the switching speed, current flow, packing density, and provides better immunity to SCEs. This thesis proposes a Cylindrical Surrounding Double-Gate (CSDG) MOSFET which is an extended version of Double-Gate (DG) MOSFET and Cylindrical Surrounding-Gate (CSG) MOSFET in terms of form factor and current drive respectively. Furthermore, employing the Evanescent-Mode analysis (EMA) of a two-dimensional (2D) Poisson solution, the performance analysis of the novel CSDG MOSFET is presented. The channel length, radii Silicon film difference, and the oxide thickness are investigated for the CSDG MOSFET at the subthreshold regime. Using the minimum channel potential expression obtained by EMA, the threshold voltage and the subthreshold swing model of the proposed CSDG MOSFET are evaluated and discussed. The device performance is verified with various values of radii Silicon film difference and gate oxide thickness Finally, the low operating power and switching characteristics of the proposed CSDG MOSFET has been employed to design a simple CSDG bridge rectifier circuit for micropower electricity (energy harvester). Similar to the traditional MOSFETs, the switching process of CSDG MOSFET is in two operating modes: switch-ON (conduction of current between the drain and source) or switched-OFF (no conduction of current). However, unlike the traditional diode bridge rectifier which utilizes four diodes for its operation, the CSDG bridge rectifier circuits employs only two CSDGs (n-channel and p- channel) for its operation. This optimizes cost and improves efficiency. Finally, the results from the analyses demonstrate that the proposed CSDG MOSFET is a promising device for nanotechnology and self-micro powered device system application

IMPACT OF HIGH-Κ METAL OXIDE AS GATE DIELECTRIC ON THE CERTAIN ELECTRICAL PROPERTIES OF SILICON NANOWIRE FIELD-EFFECT TRANSISTORS: A SIMULATION STUDY

Standard Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are gaining prominence in low-power nanoscale applications. This is largely attributed to their proximity to physical and thermal limits, rendering them a compelling option for energy-efficient electronic devices. In this study, we hypothesized that the high-κ HfO2 in a quasi-ballistic SiNW MOSFET acts as the gate dielectric. In this case, the data from the TCAD simulation and the model demonstrated exceptional agreement. The proposed model for a SiNW MOSFET with high-κ HfO2 exhibits a consistently increasing drain current, albeit with a smaller magnitude compared to a quasi-ballistic device (QBD). Additionally, it shows reduced mobility and decreased transconductance when considering the combined effects of scattering and temperature. As gate voltage increases, temperature-induced transconductance decline in SiNW MOSFETs becomes significant. Our method is suitable for modeling scattered SiNW MOSFETs with temperature effects, as TGF values are similar in the subthreshold region for both Near Ballistic and Scattered SiNW MOSFET models