Effective electrothermal analysis of electronic devices and systems with parameterized macromodeling

We propose a parameterized macromodeling methodology to effectively and accurately carry out dynamic electrothermal (ET) simulations of electronic components and systems, while taking into account the influence of key design parameters on the system behavior. In order to improve the accuracy and to reduce the number of computationally expensive thermal simulations needed for the macromodel generation, a decomposition of the frequency-domain data samples of the thermal impedance matrix is proposed. The approach is applied to study the impact of layout variations on the dynamic ET behavior of a state-of-the-art 8-finger AlGaN/GaN high-electron mobility transistor grown on a SiC substrate. The simulation results confirm the high accuracy and computational gain obtained using parameterized macromodels instead of a standard method based on iterative complete numerical analysis

Reliability Analysis of Power Electronic Devices

The thesis deals with the reliability of Power Electronic Devices to the purpose of evaluating the phenomena which mainly dictate the limiting conditions where a power device can safely operate. Reliability analyses are conducted by means of either simulations and experimental measurements

Transient out-of-SOA robustness of SiC power MOSFETs

Beyond their main function of high-frequency switches in modulated power converters, solid-state power devices are required in many application domains to also ensure robustness against a number of overload operational conditions. This paper considers the specific case of 1200 V SiC power MOSFETs and analyses their performance under three main transient regimes at the edge of and out of their Safe Operating Area: unclamped inductive switching led avalanche breakdown; short-circuit; operation as current limiting and regulating devices. The results presented highlight both inherent major strengths of SiC over Si and areas for improvement by tailored device design. The paper aims to contribute useful indications for technology development in future device generations to better match widespread and varied application requirements

Benchmarking the robustness performance of SiC cascode JFETS against contemporary devices using simulations and experimental measurements

This thesis provides the first comprehensive benchmarking exercise of SiC Cascode JFETs against similarly rated SiC Planar MOSFETs, Trench MOSFETs and other devices. Experimental measurements of short circuits in single and parallel devices, single and repetitive unclamped inductive switching as well as double pulse tests are used together with finite element simulations throughout the thesis. Power device robustness measures how well a device can sustain shocks during anomalous operation. These operating conditions are high voltages that exceed the device breakdown (avalanche conduction), or simultaneous high current and voltage through the device (Short circuit conduction). The silicon Carbide (SiC) cascode JFET is an electronic switch that combines two power devices, a low voltage silicon (Si) MOSFET and a high voltage SiC JFET operating as a single switch. This configuration avoids the challenges of reduced gate oxide reliability in SiC MOSFETs, and negative turn-on Voltage for JFETs. However, the robustness of SiC cascode JFETs have not been examined as extensively as conventional devices. Hence, this thesis investigates the robustness of SiC cascode JFETs as well as the failure modes during such operation and benchmarks the performance against conventional devices. Analysis of avalanche robustness in SiC Cascode JFETs indicated a peculiar style of failure at high temperatures characterised by a soft failure (delayed turn-off, change of current slope, and dip in voltage), and an eventual catastrophic failure. This failure is different from other devices analysed which demonstrated a single catastrophic failure. The results show that the gate resistance of the SiC JFET plays a crucial role during avalanche mode conduction. Finite element simulations confirm this observation. The Short circuit (SC) robustness analysis of the SiC Cascode JFET demonstrated invariability with temperature. In contrast, benchmarked devices show a SC correlation with temperature. The short circuit operation also revealed the Cascode JFET fails with a drain source short while the gate-source junction is still functional. Also revealed is the crucial role of increasing JFET gate resistance in reducing short circuit robustness. The SC robustness is also analysed for parallel connected devices. The analysis demonstrates the parameters with the largest impact on SC current shared between paralleled devices. Variation in the embedded JFET gate resistance within the cascode JFET presents with the highest impact as confirmed by finite element simulation, while interface charges and the doping of the CSL region present with the largest impact in SiC MOSFET

Analysis of performance of SiC bipolar semiconductor devices for grid-level converters

Recent commercialization of SiC bipolar devices, including SiC BJT, SiC MPS diode and SiC PiN diodes have enabled potential candidates to replace their SiC unipolar counterparts. However, the prospects of 4H-SiC power bipolar devices still need further investigation. This thesis compares the static and dynamic performance and reliability for the commercial SiC bipolar devices including SiC BJT, SiC MPS diode and SiC PiN diode and their similarly rated Silicon counterparts mainly by means of experimental measurements.Through comprehensive double-pulse measurements, the turn-on and turn-off transition in Silicon BJT is seen to be much slower than that of the SiC BJT while the transient time will increase with temperature and decreases with collector currents. The common-emitter current gain (β) of SiC BJT is also found to be much higher than its Silicon counterpart. Significant turn-off delay is observed in single Si BJT which becomes worse when in parallel connection as it aggravates the current mismatch across the two devices, while this delay is almost non-existent in SiC devices. The current collapse seen in single SiC BJT is mitigated by parallel connection. These are dependant on temperature and base resistance, especially in the case of Silicon BJT. The static performance of power Silicon and SiC BJT has also been evaluated. It has been found that the higher base-emitter junction voltage of SiC BJTs enables quasi-saturation mode of operation with low on-resistance, which is also the case for Silicon BJTs only at high base currents. In terms of DC gain measured under steady state operation, the observed negative temperature coefficient (NTC) of β in SiC BJTs and the positive coefficient (PTC) in Silicon BJTs can make the β of SiC BJT lower than that in Silicon at high temperatures. It has been found that parallel connection promotes both the on-state conductivity and current gain in Silicon BJTs and conductivity in SiC BJTs.The characterization of power diodes reveals that the superior switching performance of the SiC MPS & JBS diode when compared with the Si PiN diode is due to the absence of the stored charge. This also leads to the larger on-state voltage in both SiC diodes and becomes worse at high currents under high temperatures. Through comprehensive Unclamped Inductive Switching (UIS) measurements, it is seen that the avalanche ruggedness of SiC MPS & JBS diodes outperform that of the closely rated Silicon PiN diode taking advantage of the wide-bandgap properties of SiC. Higher critical avalanche energy and thus better avalanche ruggedness can also be observed in SiC JBS diode compared with the SiC MPS diode. SiC MPS diodes can compete with Si PiN diodes in terms of the surge current limits, while the SiC JBS diode failed under a lower electrothermal stress. This is observed by the dramatic increase in its reverse leakage current at lower voltages.The 15 kV SiC PiN diodes feature smaller device dimensions, less reverse recovery charge and less on-resistance when compared to the 15 kV Silicon PiN diodes. Nevertheless, when evaluating its long-term reliability by using the aggravated power cycling configuration, the high junction temperature together with the dislocation defects in the SiC PiN diode accelerate its degradation. Such degradations are not observed in Silicon PiN diodes for the same junction temperature and high-temperature stress periods

Study of Silicon Carbide Power MOSFETs Behaviour in Out-of-SOA Conditions

The need for efficient conversion and control of electrical power in many application areas has rapidly increased the demand for power devices with better and better performances. In order to go beyond the limit imposed by Silicon devices, there has always been a great interest for new materials. In recent years, Silicon Carbide Power devices, mainly power diodes and MOSFETs, have become commercially available and have begun to replace their Silicon counterpart in many application areas. The reason lays in some superior material properties that allow developing higher efficient power systems. Nevertheless, a wider spread of these devices could not be achieved without a deep analysis of the elements that might affect their reliability. The current work deals with the study of SiC Power MOSFETs reliability, with particular focus on short-circuit operation. To achieve this purpose, wide set of experiments has been carried out on commercially available devices, providing both electrical and thermal characterization. Alongside experimental evidences, TCAD simulations have been used to get a full understanding of the inner physical failure dynamics. Eventually, it has been possible to give explanation about SiC Power MOSFETs failure mechanisms. In particular, two different phenomena might occur and both are related to temperature increase inside the device

Towards a More Flexible, Sustainable, Efficient and Reliable Induction Cooking: A Power Semiconductor Device Perspective

Esta tesis tiene como objetivo fundamental la mejora de la flexibilidad, sostenibilidad, eficiencia y fiabilidad de las cocinas de inducción por medio de la utilización de dispositivos semiconductores de potencia: Dentro de este marco, existe una funcionalidad que presenta un amplio rango de mejora. Se trata de la función de multiplexación de potencia, la cual pretende resolverse de una manera más eficaz por medio de la sustitución de los comúnmente utilizados relés electromecánicos por dispositivos de estado sólido. De entre todas las posibles implementaciones, se ha identificado entre las más prometedoras a aquellas basadas en dispositivos de alta movilidad de electrones (HEMT) de Nitruro de Galio (GaN) y de aquellas basadas en Carburo de Silicio (SiC), pues presentan unas características muy superiores a los relés a los que se pretende sustituir. Por el contrario, otras soluciones que inicialmente parecían ser muy prometedoras, como los MOSFETs de Súper-Unión, han presentado una serie de comportamientos anómalos, que han sido estudiados minuciosamente por medio de simulaciones físicas a nivel de chip. Además, se analiza en distintas condiciones la capacidad en cortocircuito de dispositivos convencionalmente empleados en cocinas de inducción, como son los IGBTs, tratándose de encontrar el equilibrio entre un comportamiento robusto al tiempo que se mantienen bajas las pérdidas de potencia. Por otra parte, también se estudia la robustez y fiabilidad de varios GaN HEMT de 600- 650 V tanto de forma experimental como por medio de simulaciones físicas. Finalmente se aborda el cálculo de las pérdidas de potencia en convertidores de potencia resonantes empleando técnicas de termografía infrarroja. Por medio de esta técnica no solo es posible medir de forma precisa las diferentes contribuciones de las pérdidas, sino que también es posible apreciar cómo se distribuye la corriente a nivel de chip cuando, por ejemplo, el componente opera en modo de conmutación dura. Como resultado, se obtiene información relevante relacionada con modos de fallo. Además, también ha sido aprovechar las caracterizaciones realizadas para obtener un modelo térmico de simulación.This thesis is focused on addressing a more flexible, sustainable, efficient and reliable induction cooking approach from a power semiconductor device perspective. In this framework, this PhD Thesis has identified the following activities to cover such demands: In view of the growing interest for an effective power multiplexing in Induction Heating (IH) applications, improved and efficient Solid State Relays (SSRs) as an alternative to the electromechanical relays (EMRs) are deeply investigated. In this context, emerging Gallium Nitride (GaN) High‐Electron‐Mobility Transistors (GaN HEMTs) and Silicon Carbide (SiC) based devices are identified as potential candidates for the mentioned application, featuring several improved characteristics over EMRs. On the contrary, other solutions, which seemed to be very promising, resulted to suffer from anomalous behaviors; i.e. SJ MOSFETs are thoroughly analysed by electro‐thermal physical simulations at the device level. Additionally, the Short Circuit (SC) capability of power semiconductor devices employed or with potential to be used in IH appliances is also analysed. On the one hand, conventional IGBTs SC behavior is evaluated under different test conditions so that to obtain the trade‐off between ruggedness and low power losses. Moreover, ruggedness and reliability of several normally‐off 600‐650 V GaN HEMTs are deeply investigated by experimentation and physics‐based simulation. Finally, power losses calculation at die‐level is performed for resonant power converters by means of using Infrared Thermography (IRT). This method assists to determine, at the die‐level, the power losses and current distribution in IGBTs used in resonant soft‐switching power converters when functioning within or outside the Zero Voltage Switching (ZVS) condition. As a result, relevant information is obtained related to decreasing the power losses during commutation in the final application, and a thermal model is extracted for simulation purposes.<br /