Topological issues in single phase power factor correction

The equipment connected to an electricity distribution network usually needs some kind of power conditioning, typically rectification, which produces a non-sinusoidal line current due to the nonlinear input characteristic. With the steadily increasing use of such equipment, line current harmonics have become a significant problem. Their adverse effects on the power system are well recognized. They include increased magnitudes of neutral currents in three- phase systems, overheating in transformers and induction motors, as well as the degradation of system voltage waveforms. Several international standards now exist, which limit the harmonic content due to line currents of equipment connected to electricity distribution networks. As a result, there is the need for a reduction in line current harmonics, or Power Factor Correction - PFC. There are two types of PFC’s. 1) Passive PFC, 2) Active PFC. The active PFC is further classified into low-frequency and high-frequency active PFC depending on the switching frequency. Different techniques in passive PFC and active PFC are presented here. Among these PFC’s we will get better power factor by using high-frequency active PFC circuit. Any DC-DC converters can be used for this purpose, if a suitable control method is used to shape its input current or if it has inherent PFC properties. The DC-DC converters can operate in Continuous Inductor Current Mode – CICM, where the inductor current never reaches zero during one switching cycle or Discontinuous Inductor Current Mode - DICM, where the inductor current is zero during intervals of the switching cycle. In DICM, the input inductor is no longer a state variable since its state in a given switching cycle is independent on the value in the previous switching cycle. The peak of the inductor current is sampling the line voltage automatically. This property of DICM input circuit can be called “self power factor correction” because no control loop is required from its input side. In CICM, different control techniques are used to control the inductor current. Some of them are (1) peak current control (2) average current control (3) Hysteresis control (4) borderline control. These control techniques specifically developed for PFC boost converters are analyzed. For each control strategy advantages and drawbacks are highlighted and information on available commercial IC's is given. This high frequency switching PFC stage also has drawbacks, such as: it introduces additional losses, thus reducing the overall efficiency; it increases the EMI, due to the highfrequency content of the input current. Some of the EMI requirements are discussed. But the level of high-frequency EMI is much higher with a considerable amount of conduction and switching losses. This highfrequency EMI will be eliminated by introducing an EMI filter in between AC supply and the diode bridge rectifier. The efficiency will be improved by reducing the losses using soft switching techniques such as ‘Zero Voltage Switching’- (ZVS), ‘Zero Voltage Transition’ (ZVT), and ‘Zero Current Switching’- (ZCS). We study circuit techniques to improve the efficiency of the PFC stage by lowering the conduction losses and/or the switching losses. Operation of a ZVT converter will be discussed, in which the switching losses of the auxiliary switch are minimized by using an additional circuit applied to the auxiliary switch. Besides the main switch ZVS turned- on and turned-off, and the auxiliary switch ZCS turned-on and turned-off near ZVS. Since the active switch is turned- on and turned-off softly, the switching losses are reduced and the higher efficiency of the system is achieved

Digital enhancement techniques for fractional-N frequency synthesizers

Meeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing the data traffic generated by trillions of such nodes also puts severe energy constraints on the data centers. Clock generators that are essential elements in these systems consume significant power and therefore must be optimized for low power and high performance. The focus of this thesis is on improving the energy efficiency of frequency synthesizers and clocking modules by exploring design techniques at both the architectural and circuit levels. In the first part of this work, a digital fractional-N phase locked loop (FNPLL) that employs a high resolution time-to-digital converter (TDC) and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1ps resolution. Fabricated in 65nm CMOS process, the prototype PLL achieves better than -106dBc/Hz in-band noise and 3MHz PLL bandwidth at 4.5GHz output frequency using 50MHz reference. The PLL achieves excellent jitter performance of 490fsrms, while consumes only 3.7mW. This translates to the best reported jitter-power figure-of-merit (FoM) of -240.5dB among previously reported FNPLLs. Phase noise performance of ring oscillator based digital FNPLLs is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the TDC, ΔΣ fractional divider, and digital-to-analog converter (DAC). As a consequence, their FoM that quantifies the power-jitter tradeoff is at least 25dB worse than their LC-oscillator based FNPLL counterparts. In the second part of this thesis, we seek to close this performance gap by extending PLL bandwidth using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. A prototype was implemented in a 65nm CMOS process operating over a wide frequency range of 2.0GHz-5.5GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9psrms integrated jitter while consuming only 4mW at 5GHz output. The measured in-band phase noise is better than -96 dBc/Hz at 1MHz offset. The proposed FNPLL achieves wide bandwidth up to 6MHz using a 50 MHz reference and its FoM is -228.5dB, which is at about 20dB better than previously reported ring-based digital FNPLLs. In the third part, we propose a new multi-output clock generator architecture using open loop fractional dividers for system-on-chip (SoC) platforms. Modern multi-core processors use per core clocking, where each core runs at its own speed. The core frequency can be changed dynamically to optimize for performance or power dissipation using a dynamic frequency scaling (DFS) technique. Fast frequency switching is highly desirable as long as it does not interrupt code execution; therefore it requires smooth frequency transitions with no undershoots. The second main requirement in processor clocking is the capability of spread spectrum frequency modulation. By spreading the clock energy across a wide bandwidth, the electromagnetic interference (EMI) is dramatically reduced. A conventional PLL clock generation approach suffers from a slow frequency settling and limited spread spectrum modulation capabilities. The proposed open loop fractional divider architecture overcomes the bandwidth limitation in fractional-N PLLs. The fractional divider switches the output frequency instantaneously and provides an excellent spread spectrum performance, where precise and programmable modulation depth and frequency can be applied to satisfy different EMI requirements. The fractional divider has unlimited modulation bandwidth resulting in spread spectrum modulation with no filtering, unlike fractional-N PLL; consequently it achieves higher EMI reduction. A prototype fractional divider was implemented in a 65nm CMOS process, where the measured peak-to-peak jitter is less than 27ps over a wide frequency range from 20MHz to 1GHz. The total power consumption is about 3.2mW for 1GHz output frequency. The all-digital implementation of the divider occupies the smallest area of 0.017mm2 compared to state-of-the-art designs. As the data rate of serial links goes higher, the jitter requirements of the clock generator become more stringent. Improving the jitter performance of conventional PLLs to less than (200fsrms) always comes with a large power penalty (tens of mWs). This is due to the PLL coupled noise bandwidth trade-off, which imposes stringent noise requirements on the oscillator and/or loop components. Alternatively, an injection-locked clock multiplier (ILCM) provides many advantages in terms of phase noise, power, and area compared to classical PLLs, but they suffer from a narrow lock-in range and a high sensitivity to PVT variations especially at a large multiplication factor (N). In the fourth part of this thesis, a low-jitter, low-power LC-based ILCM with a digital frequency-tracking loop (FTL) is presented. The proposed FTL relies on a new pulse gating technique to continuously tune the oscillator's free-running frequency. The FTL ensures robust operation across PVT variations and resolves the race condition existing in injection locked PLLs by decoupling frequency tuning from the injection path. As a result, the phase locking condition is only determined by the injection path. This work also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO's lock-in range, and the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of 0.25mm2. The prototype ILCM multiplies the reference frequency by 64 to generate an output clock in the range of 6.75GHz-8.25GHz. A superior jitter performance of 190fsrms is achieved, while consuming only 2.25mW power. This translates to a best FoM of -251dB. Unlike conventional PLLs, ILCMs have been fundamentally limited to only integer-N operation and cannot synthesize fractional-N frequencies. In the last part of this thesis, we extend the merits of ILCMs to fractional-N and overcome this fundamental limitation. We employ DTC-based QNC techniques in order to align injected pulses to the oscillator's zero crossings, which enables it to pull the oscillator toward phase lock, thus realizing a fractional-N ILCM. Fabricated in 65nm CMOS process, a prototype 20-bit fractional-N ILCM with an output range of 6.75GHz-8.25GHz consumes only 3.25mW. It achieves excellent jitter performance of 110fsrms and 175fsrms in integer- and fractional-N modes respectively, which translates to the best-reported FoM in both integer- (-255dB) and fractional-N (-252dB) modes. The proposed fractional-N ILCM also features the first-reported rapid on/off capability, where the transient absolute jitter performance at wake-up is bounded below 4ps after less than 4ns. This demonstrates almost instantaneous phase settling. This unique capability enables tremendous energy saving by turning on the clock multiplier only when needed. This energy proportional operation leverages idle times to save power at the system-level of wireline and wireless transceivers

A wideband low-power continuous-time delta-sigma modulator for next generation wireless applications

Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are widely used in wireless transceivers. Recently, continuous-time (CT) ΔΣ ADCs gain growing interest in wireless applications for their lower power consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts. In this thesis, a wideband low-power CT ΔΣ modulator for next generation wireless applications is proposed to achieve 10-bit dynamic range within a 25 MHz signal bandwidth. On the system level, a low-power, mainly feed-forward architecture is used to realize the loop filter. Feed-in branches are added and optimized to eliminate the out-of-band peaking in the signal transfer function. On the circuit level, two-stage operational amplifiers with class-AB output stages are used to implement low-power active RC integrators. Capacitor tuning is used to compensate the variation of RC time constants. In addition, a fast current adder, an 11-level internal flash ADC and three current feedback DACs are also integrated on the chip which was manufactured in TSMC 0.18 μm CMOS technology. The test results show that the modulator draws less than 10 mA from the 1.8 V supply voltage

Crexens™: an expandable general-purpose electrochemical analyzer

2019 Fall.Includes bibliographical references.Electrochemical analysis has gained a great deal of attention of late due to its low-cost, easy-to-perform, and easy-to-miniaturize, especially in personal health care where accuracy and mobility are key factors to bring diagnostics to patients. According to data from Centers for Medicare & Medicaid Services (CMS) in the US, the share of health expenditure in the US has been kept growing in the past 3 decades and reached 17.9% of its overall Gross Domestic Product till 2016, which is equivalent to $10,348 for every person in the US per year. On the other hand, health care resources are often limited not only in rural area but also appeared in well-developed countries. The urgent need and the lack of health resource brings to front the research interest of Point-of-Care (PoC) diagnosis devices. Electrochemical methods have been largely adopted by chemist and biologist for their research purposes. However, several issues exist within current commercial benchtop instruments for electrochemical measurement. First of all, the current commercial instruments are usually bulky and do not have handheld feature for point-of-care applications and the cost are easily near$5,000 each or above. Secondly, most of the instruments do not have good integration level that can perform different types of electrochemical measurements for different applications. The last but not the least, the existing generic benchtops instruments for electrochemical measurements have complex operational procedures that require users to have a sufficient biochemistry and electrochemistry background to operate them correctly. The proposed Crexens™ analyzer platform is aimed to present an affordable electrochemical analyzerwhile achieving comparable performance to the existing commercial instruments, thus, making general electrochemical measurement applications accessible to general public. In this dissertation, the overall Crexens™ electrochemical analyzer architecture and its evolution are presented. The foundation of the Crexens™ architecture was derived from two separate but related research in electrochemical sensing. One of them is a microelectrode sensor array using CMOS for neurotransmitter sensing; the other one is a DNA affinity-based capacitive sensor for infectious disease, such as ZIKA. The CMOS microelectrode sensor array achieved a 320uM sensitivity for norepinephrine, whereas the capacitive sensor achieved a dynamic range of detection from 1 /uL to 105 /uL target molecules (20 to 2 million targets), which makes it be within the detection range in a typical clinical application environment. This dissertation also covers the design details of the CMOS microelectrode array sensor and the capacitive sensor design as a prelude to the development of the Crexens™ analyzer architecture. Finally, an expandable integrated electrochemical analyzer architecture (Crexens™) has been designed for mobile point-of-care (POC) applications. Electrochemical methods have been explored in detecting various bio-molecules such as glucose, lactate, protein, DNA, neurotransmitter, steroid hormone, which resulted in good sensitivity and selectivity. The proposed system is capable of running electrochemical experiments including cyclic voltammetry (CV), electrochemical impedance spectroscopy (EIS), electrochemical capacitive spectroscopy (ECS), amperometry, potentiometry, and other derived electrochemical based tests. This system consist of a front-end interface to sensor electrodes, a back-end user interface on smart phone and PC, a base unit as master module, a low-noise add-on module, a high-speed add-on module, and a multi-channel add-on module. The architecture allows LEGO™-like capability to stack add-on modules on to the base-unit for performance enhancements in noise, speed or parallelism. The analyzer is capable of performing up to 1900 V/s CV with 10 mV step, up to 12 kHz EIS scan range and a limit of detection at 637 pA for amperometric applications with the base module. With high performance module, the EIS scan range can be extended upto 5 MHz. The limit of detection can be further improved to be at 333 fA using the low-noise module. The form factor of the electrochemical analyzer is designed for its mobile/point-of-care applications, integrating its entire functionality on to a 70 cm² area of surface space. A glutamine enzymatic sensor was used to valid the capability of the proposed electrochemical analyzer and turned out to give good linearity and reached a limit of detection at 50 uM

Recent Topics in Electromagnetic Compatibility

Recent Topics in Electromagnetic Compatability discusses several topics in electromagnetic compatibility (EMC) and electromagnetic interference (EMI), including measurements, shielding, emission, interference, biomedical devices, and numerical modeling. Over five sections, chapters address the electromagnetic spectrum of corona discharge, life cycle assessment of flexible electromagnetic shields, EMC requirements for implantable medical devices, analysis and design of absorbers for EMC applications, artificial surfaces, and media for EMC and EMI shielding, and much more

LASER Tech Briefs, September 1993

This edition of LASER Tech briefs contains a feature on photonics. The other topics include: Electronic Components and Circuits. Electronic Systems, Physical Sciences, Materials, Computer Programs, Mechanics, Machinery, Fabrication Technology, Mathematics and Information Sciences, Life Sciences and books and reports

ENABLING HARDWARE TECHNOLOGIES FOR AUTONOMY IN TINY ROBOTS: CONTROL, INTEGRATION, ACTUATION

The last two decades have seen many exciting examples of tiny robots from a few cm3 to less than one cm3. Although individually limited, a large group of these robots has the potential to work cooperatively and accomplish complex tasks. Two examples from nature that exhibit this type of cooperation are ant and bee colonies. They have the potential to assist in applications like search and rescue, military scouting, infrastructure and equipment monitoring, nano-manufacture, and possibly medicine. Most of these applications require the high level of autonomy that has been demonstrated by large robotic platforms, such as the iRobot and Honda ASIMO. However, when robot size shrinks down, current approaches to achieve the necessary functions are no longer valid. This work focused on challenges associated with the electronics and fabrication. We addressed three major technical hurdles inherent to current approaches: 1) difficulty of compact integration; 2) need for real-time and power-efficient computations; 3) unavailability of commercial tiny actuators and motion mechanisms. The aim of this work was to provide enabling hardware technologies to achieve autonomy in tiny robots. We proposed a decentralized application-specific integrated circuit (ASIC) where each component is responsible for its own operation and autonomy to the greatest extent possible. The ASIC consists of electronics modules for the fundamental functions required to fulfill the desired autonomy: actuation, control, power supply, and sensing. The actuators and mechanisms could potentially be post-fabricated on the ASIC directly. This design makes for a modular architecture. The following components were shown to work in physical implementations or simulations: 1) a tunable motion controller for ultralow frequency actuation; 2) a nonvolatile memory and programming circuit to achieve automatic and one-time programming; 3) a high-voltage circuit with the highest reported breakdown voltage in standard 0.5 μm CMOS; 4) thermal actuators fabricated using CMOS compatible process; 5) a low-power mixed-signal computational architecture for robotic dynamics simulator; 6) a frequency-boost technique to achieve low jitter in ring oscillators. These contributions will be generally enabling for other systems with strict size and power constraints such as wireless sensor nodes

Intelligent Circuits and Systems

ICICS-2020 is the third conference initiated by the School of Electronics and Electrical Engineering at Lovely Professional University that explored recent innovations of researchers working for the development of smart and green technologies in the fields of Energy, Electronics, Communications, Computers, and Control. ICICS provides innovators to identify new opportunities for the social and economic benefits of society.　 This conference bridges the gap between academics and R&D institutions, social visionaries, and experts from all strata of society to present their ongoing research activities and foster research relations between them. It provides opportunities for the exchange of new ideas, applications, and experiences in the field of smart technologies and finding global partners for future collaboration. The ICICS-2020 was conducted in two broad categories, Intelligent Circuits & Intelligent Systems and Emerging Technologies in Electrical Engineering