Radix-2 x 2 x 2 algorithm for the 3-D discrete hartley transform

The discrete Hartley transform (DHT) has proved to be a valuable tool in digital signal/image processing and communications and has also attracted research interests in many multidimensional applications. Although many fast algorithms have been developed for the calculation of one- and two-dimensional (1-D and 2-D) DHT, the development of multidimensional algorithms in three and more dimensions is still unexplored and has not been given similar attention; hence, the multidimensional Hartley transform is usually calculated through the row-column approach. However, proper multidimensional algorithms can be more efficient than the row-column method and need to be developed. Therefore, it is the aim of this paper to introduce the concept and derivation of the three-dimensional (3-D) radix-2 2X 2X algorithm for fast calculation of the 3-D discrete Hartley transform. The proposed algorithm is based on the principles of the divide-and-conquer approach applied directly in 3-D. It has a simple butterfly structure and has been found to offer significant savings in arithmetic operations compared with the row-column approach based on similar algorithms

New Decimation-In-Time Fast Hartley Transform Algorithm

This paper presents a new algorithm for fast calculation of the discrete Hartley transform (DHT) based on decimation-in-time (DIT) approach. The proposed radix-2^2 fast Hartley transform (FHT) DIT algorithm has a regular butterfly structure that provides flexibility of different powers-of-two transform lengths, substantially reducing the arithmetic complexity with simple bit reversing for ordering the output sequence. The algorithm is developed through the three-dimensional linear index map and by integrating two stages of the signal flow graph together into a single butterfly. The algorithm is implemented and its computational complexity has been analysed and compared with the existing FHT algorithms, showing that it is significantly reduce the structural complexity with a better indexing scheme that is suitable for efficient implementation

Perfect reconstruction QMF banks for two-dimensional applications

A theory is outlined whereby it is possible to design a M x N channel two-dimensional quadrature mirror filter bank which has perfect reconstruction property. Such a property ensures freedom from aliasing, amplitude distortion, and phase distortion. The method is based on a simple property of certain transfer matrices, namely the losslessness property

Direct split-radix algorithm for fast computation of type-II discrete Hartley transform

In this paper, a novel split-radix algorithm for fast calculation the discrete Hartley transform of type-II (DHT-II) is intoduced. The algorithm is established through the decimation in time (DIT) approach, and implementedby splitting a length N of DHT-II into one DHT-II of length N/2 for even-indexed samples and two DHTs-II of length N/4 for odd-indexed samples. The proposed algorithm possesses the desired properties such as regularity, inplace calculation and it is represented by simple closed form decomposition sleading to considerable reductions in the arithmetic complexity compared to the existing DHT-II algorithms. Additionally, the validity of the proposed algorithm has been confirmed through analysing the arithmetic complexityby calculating the number of real additions and multiplications and associating it with the existing DHT-II algorithms

Efficient fast hartley transform algorithms for hypercube-connected multicomputers

Cataloged from PDF version of article.Although fast Hartley transform (FHT) provides efficient spectral analysis of real discrete signals, the literature that addresses the parallelization of FHT is extremely rare. FHT is a real transformation and does not necessitate any complex arithmetics. On the other hand, FHT algorithm has an irregular computational structure which makes efficient parallelization harder. In this paper, we propose a efficient restructuring for the sequential FHT algorithm which brings regularity and symmetry to the computational structure of the FHT. Then, we propose an efficient parallel FHT algorithm for medium-to-coarse grain hypercube multicomputers by introducing a dynamic mapping scheme for the restructured FHT. The proposed parallel algorithm achieves perfect load-balance, minimizes both the number and volume of concurrent communications, allows only nearestneighbor communications and achieves in-place computation and communication. The proposed algorithm is implemented on a 32- node iPSC12' hypercube multicomputer. High-efficiency values are obtained even for small size FHT problems

DFT algorithms for bit-serial GaAs array processor architectures

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology

Efficient parallel digital signal processing algorithms for hypercube-connected multicomputers

Ankara : Department of Computer Engineering and Information Science and Institute of Engineering and Science, Bilkent Univ., 1992.Thesis (Master's) -- Bilkent University, 1992.Includes bibliographical references leaves 88-91In this thesis, efficient parallelization of Digital Signal Processing (DSP) algorithms, (FFT, FHT and FCT), on multicomputers implementing the hypercube interconnection topology are investigated. The proposed algorithms, maintain perfect load-balance, minimize communication overhead, can overlap communications with computations and achieve regular computational patterns. The proposed parallel algorithms are implemented on Intel’s iPSC/2^ hypercube multicomputer with 32 processors. High efficiency and almost linear speedup values are obtained for even small size problems.Derviş, ArgunM.S

Mengenal pasti tahap pengetahuan pelajar tahun akhir Ijazah Sarjana Muda Kejuruteraan di KUiTTHO dalam bidang keusahawanan dari aspek pengurusan modal

Malaysia ialah sebuah negara membangun di dunia. Dalam proses pembangunan ini, hasrat negara untuk melahirkan bakal usahawan beijaya tidak boleh dipandang ringan. Oleh itu, pengetahuan dalam bidang keusahawanan perlu diberi perhatian dengan sewajarnya; antara aspek utama dalam keusahawanan ialah modal. Pengurusan modal yang tidak cekap menjadi punca utama kegagalan usahawan. Menyedari hakikat ini, kajian berkaitan Pengurusan Modal dijalankan ke atas 100 orang pelajar Tahun Akhir Kejuruteraan di KUiTTHO. Sampel ini dipilih kerana pelajar-pelajar ini akan menempuhi alam pekeijaan di mana mereka boleh memilih keusahawanan sebagai satu keijaya. Walau pun mereka bukanlah pelajar dari jurusan perniagaan, namun mereka mempunyai kemahiran dalam mereka cipta produk yang boleh dikomersialkan. Hasil dapatan kajian membuktikan bahawa pelajar-pelajar ini berminat dalam bidang keusahawanan namun masih kurang pengetahuan tentang pengurusan modal terutamanya dalam menentukan modal permulaan, pengurusan modal keija dan caracara menentukan pembiayaan kewangan menggunakan kaedah jualan harian. Oleh itu, satu garis panduan Pengurusan Modal dibina untuk memberi pendedahan kepada mereka

Energy efficient hardware acceleration of multimedia processing tools

The world of mobile devices is experiencing an ongoing trend of feature enhancement and generalpurpose multimedia platform convergence. This trend poses many grand challenges, the most pressing being their limited battery life as a consequence of delivering computationally demanding features. The envisaged mobile application features can be considered to be accelerated by a set of underpinning hardware blocks Based on the survey that this thesis presents on modem video compression standards and their associated enabling technologies, it is concluded that tight energy and throughput constraints can still be effectively tackled at algorithmic level in order to design re-usable optimised hardware acceleration cores. To prove these conclusions, the work m this thesis is focused on two of the basic enabling technologies that support mobile video applications, namely the Shape Adaptive Discrete Cosine Transform (SA-DCT) and its inverse, the SA-IDCT. The hardware architectures presented in this work have been designed with energy efficiency in mind. This goal is achieved by employing high level techniques such as redundant computation elimination, parallelism and low switching computation structures. Both architectures compare favourably against the relevant pnor art in the literature. The SA-DCT/IDCT technologies are instances of a more general computation - namely, both are Constant Matrix Multiplication (CMM) operations. Thus, this thesis also proposes an algorithm for the efficient hardware design of any general CMM-based enabling technology. The proposed algorithm leverages the effective solution search capability of genetic programming. A bonus feature of the proposed modelling approach is that it is further amenable to hardware acceleration. Another bonus feature is an early exit mechanism that achieves large search space reductions .Results show an improvement on state of the art algorithms with future potential for even greater savings