System level power integrity transient analysis using a physics-based approach

With decreasing supply voltage level and massive demanding current on system chipset, power integrity design becomes more and more critical for system stability. The ultimate goal of well-designed power delivery network (PDN) is to deliver desired voltage level from the source to destination, in other words, to minimize voltage noise delivered to digital devices. The thesis is composed of three parts. The first part focuses on-die level power models including simplified chip power model (CPM) for system level analysis and the worst scenario current profile. The second part of this work introduces the physics-based equivalent circuit model to simplify the passive PDN model to RLC circuit netlist, to be compatible with any spice simulators and tremendously boost simulation speed. Then a novel system/chip level end-to-end transient model is proposed, including the die model and passive PDN model discussed in previous two chapters as well as a SIMPLIS based small signal VRM model. In the last part of the thesis, how to model voltage regulator module (VRM) is explicitly discussed. Different linear approximated VRM modeling approaches have been compared with the SIMPLIS small signal VRM model in both frequency domain and time domain. The comparison provides PI engineers a guideline to choose specific VRM model under specific circumstances. Finally yet importantly, a PDN optimization example was given. Other than previous PDN optimization approaches, a novel hybrid target impedance concept was proposed in this thesis, in order to improve system level PDN optimization process --Abstract, page iv

Surrogate-based Analysis and Design Optimization of Power Delivery Networks

As microprocessor architectures continue to increase computing performance under low-energy consumption, the combination of signal integrity, electromagnetic interference, and power delivery is becoming crucial in the computer industry. In this context, power delivery engineers make use of complex and computationally expensive models that impose time-consuming industrial practices to reach an adequate power delivery design. In this paper, we propose a general surrogate-based methodology for fast and reliable analysis and design optimization of power delivery networks (PDN). We first formulate a generic surrogate model methodology exploiting passive lumped models optimized by parameter extraction to fit PDN impedance profiles. This PDN modeling formulation is illustrated with industrial laboratory measurements of a 4th generation server CPU motherboard. We next propose a black box PDN surrogate modeling methodology for efficient and reliable power delivery design optimization. To build our black box PDN surrogate, we compare four metamodeling techniques: support vector machines, polynomial surrogate modeling, generalized regression neural networks, and Kriging. The resultant best metamodel is then used to enable fast and accurate optimization of the PDN performance. Two examples validate our surrogate-based optimization approach: a voltage regulator with dual power rail remote sensing intended for communications and storage applications, by finding optimal sensing resistors and loading conditions; and a multiphase voltage regulator from a 6th generation Intel® server motherboard, by finding optimal compensation settings to reduce the number of bulk capacitors without losing CPU performance.ITESO, A.C

34th Midwest Symposium on Circuits and Systems-Final Program

Organized by the Naval Postgraduate School Monterey California. Cosponsored by the IEEE Circuits and Systems Society. Symposium Organizing Committee: General Chairman-Sherif Michael, Technical Program-Roberto Cristi, Publications-Michael Soderstrand, Special Sessions- Charles W. Therrien, Publicity: Jeffrey Burl, Finance: Ralph Hippenstiel, and Local Arrangements: Barbara Cristi

Addressing Computational Complexity of High Speed Distributed Circuits Using Model Order Reduction

Advanced in the fabrication technology of integrated circuits (ICs) over the last couple of years has resulted in an unparalleled expansion of the functionality of microelectronic systems. Today’s ICs feature complex deep-submicron mixed-signal designs and have found numerous applications in industry due to their lower manufacturing costs and higher performance levels. The tendency towards smaller feature sizes and increasing clock rates is placing higher demands on signal integrity design by highlighting previously negligible interconnect effects such as distortion, reflection, ringing, delay, and crosstalk. These effects if not predicted in the early stages of the design cycle can severely degrade circuit performance and reliability. The objective of this thesis is to develop new model order reduction (MOR) techniques to minimize the computational complexity of non-linear circuits and electronic systems that have delay elements. MOR techniques provide a mechanism to generate reduced order models from the detailed description of the original modified nodal analysis (MNA) formulation. The following contributions are made in this thesis: 1. The first project presents a methodology for reduction of Partial Element Equivalent Circuit (PEEC) models. PEEC method is widely used in electromagnetic compatibility and signal integrity problems in both the time and frequency domains. The PEEC model with retardation has been applied to 3-D analysis but often result in large and dense matrices, which are computationally expensive to solve. In this thesis, a new moment matching technique based on Multi-order Arnoldi is described to model PEEC networks with retardation. 2. The second project deals with developing an efficient model order reduction algorithm for simulating large interconnect networks with nonlinear elements. The proposed methodology is based on a multidimensional subspace method and uses constraint equations to link the nonlinear elements and biasing sources to the reduced order model. This approach significantly improves the simulation time of distributed nonlinear systems, since additional ports are not required to link the nonlinear elements to the reduced order model, yielding appreciable savings in the size of the reduced order model and computational time. 3. A parameterized reduction technique for nonlinear systems is presented. The proposed method uses multidimensional subspace and variational analysis to capture the variances of design parameters and approximates the weakly nonlinear functions as a Taylor series. An SVD approach is presented to address the efficiency of reduced order model. The proposed methodology significantly improves the simulation time of weakly nonlinear systems since the size of the reduced system is smaller than the original system and a new reduced model is not required each time a design parameter is changed

Development of Multiport Single Stage Bidirectional Converter for Photovoltaic and Energy Storage Integration

The energy market is on the verge of a paradigm shift as the emergence of renewable energy sources over traditional fossil fuel based energy supply has started to become cost competitive and viable. Unfortunately, most of the attractive renewable sources come with inherent challenges such as: intermittency and unreliability. This is problematic for today\u27s stable, day ahead market based power system. Fortunately, it is well established that energy storage devices can compensate for renewable sources shortcomings. This makes the integration of energy storage with the renewable energy sources, one of the biggest challenges of modern distributed generation solution. This work discusses, the current state of the art of power conversion systems that integrate photovoltaic and battery energy storage systems. It is established that the control of bidirectional power flow to the energy storage device can be improved by optimizing its modulation and control. Traditional multistage conversion systems offers the required power delivery options, but suffers from a rigid power management system, reduced efficiency and increased cost. To solve this problem, a novel three port converter was developed which allows bidirectional power flow between the battery and the load, and unidirectional power flow from the photovoltaic port. The individual two-port portions of the three port converter were optimized in terms of modulation scheme. This leads to optimization of the proposed converter, for all possible power flow modes. In the second stage of the project, the three port converter was improved both in terms of cost and efficiency by proposing an improved topology. The improved three port converter has reduced functionality but is a perfect fit for the targeted microinverter application. The overall control system was designed to achieve improved reference tracking for power management and output AC voltage control. The bidirectional converter and both the proposed three port converters were analyzed theoretically. Finally, experimental prototypes were built to verify their performance

Development of a 5V Digital Cell Library for use with the Peregrine Semiconductor Silicon-on-Sapphire Process

The scope of the thesis work presented here is to develop a standard digital cell library operable at 5V of power supply and up to the temperatures of 125C using Peregrine 0.5m2 3.3V CMOS process. Peregrine 0.5m process was selected as a result of its availability via commercial foundry at moderate cost radiation and high temperature tolerant properties. Testing data was obtained showing no measurable gate tunneling at gate voltages below 8.5V and no source to drain avalanche below 5.5V ensuring safe operation below the 5V design corners of 5.5V. Device geometries are selected to meet drive current requirement of 1mA and acceptable Ion/Ioff ratios at high temperature. Layouts for cells, schematic, symbolic and abstract views were generated. Timing, power and area characterization data is realized in several formats compatible with Cadence and Synopsys synthesizer, place & route and simulation tools. A test chip for delay chains with single input and multi-input combinatorial gates were designed and fabricated as a part of the validation on silicon. Measured data at room temperature is well in agreement with SignalStorm's data. At 125C, delay chains performed faster in silicon by up to 25% as compared with simulated data obtained using typical model. Device characteristics for rn and rp device are obtained and percentage variations in their Id-Vd characteristics with models are calculated. Variation in test data for the test chip as compared to the simulated data is observed to be consistent with the device current variation plotted across process corners. Adherence of the targeted design specifications (from simulation) with the actual measured values verifies the cell library's functionality, timing and power parameters.School of Electrical & Computer Engineerin

Delay Extraction based Macromodeling with Parallel Processing for Efficient Simulation of High Speed Distributed Networks

This thesis attempts to address the computational demands of accurate modeling of high speed distributed networks such as interconnect networks and power distribution networks. In order to do so, two different approaches towards modeling of high speed distributed networks are considered. One approach deals with cases where the physical characteristics of the network are not known and the network is characterized by its frequency domain tabulated data. Such examples include long interconnect networks described by their Y parameter data. For this class of problems, a novel delay extraction based IFFT algorithm has been developed for accurate transient response simulation. The other modeling approach is based on a detailed knowledge of the physical and electrical characteristics of the network and assuming a quasi transverse mode of propagation of the electromagnetic wave through the network. Such problems may include two dimensional (2D) and three dimensional (3D) power distribution networks with known geometry and materials. For this class of problem, a delay extraction based macromodeling approaches is proposed which has been found to be able to capture the distributed effects of the network resulting in more compact and accurate simulation compared to the state-of-the-art quasi-static lumped models. Furthermore, waveform relaxation based algorithms for parallel simulations of large interconnect networks and 2D power distribution networks is also presented. A key contribution of this body of work is the identification of naturally parallelizable and convergent iterative techniques that can divide the computational costs of solving such large macromodels over a multi-core hardware

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc