DESIGN AUTOMATION FOR LOW POWER RFID TAGS

Radio Frequency Identification (RFID) tags are small, wireless devices capable of automated item identification, used in a variety of applications including supply chain management, asset management, automatic toll collection (EZ Pass), etc. However, the design of these types of custom systems using the traditional methods can take months for a hardware engineer to develop and debug. In this dissertation, an automated, low-power flow for the design of RFID tags has been developed, implemented and validated. This dissertation presents the RFID Compiler, which permits high-level design entry using a simple description of the desired primitives and their behavior in ANSI-C. The compiler has different back-ends capable of targeting microprocessor-based or custom hardware-based tags. For the hardware-based tag, the back-end automatically converts the user-supplied behavior in C to low power synthesizable VHDL optimized for RFID applications. The compiler also integrates a fast, high-level power macromodeling flow, which can be used to generate power estimates within 15% accuracy of industry CAD tools and to optimize the primitives and / or the behaviors, compared to conventional practices. Using the RFID Compiler, the user can develop the entire design in a matter of days or weeks. The compiler has been used to implement standards such as ANSI, ISO 18000-7, 18000-6C and 18185-7. The automatically generated tag designs were validated by targeting microprocessors such as the AD Chips EISC and FPGAs such as Xilinx Spartan 3. The corresponding ASIC implementation is comparable to the conventionally designed commercial tags in terms of the energy and area. Thus, the RFID Compiler permits the design of power efficient, custom RFID tags by a wider audience with a dramatically reduced design cycle

SysMART Indoor Services: A System of Smart and Connected Supermarkets

Smart gadgets are being embedded almost in every aspect of our lives. From smart cities to smart watches, modern industries are increasingly supporting the Internet of Things (IoT). SysMART aims at making supermarkets smart, productive, and with a touch of modern lifestyle. While similar implementations to improve the shopping experience exists, they tend mainly to replace the shopping activity at the store with online shopping. Although online shopping reduces time and effort, it deprives customers from enjoying the experience. SysMART relies on cutting-edge devices and technology to simplify and reduce the time required during grocery shopping inside the supermarket. In addition, the system monitors and maintains perishable products in good condition suitable for human consumption. SysMART is built using state-of-the-art technologies that support rapid prototyping and precision data acquisition. The selected development environment is LabVIEW with its world-class interfacing libraries. The paper comprises a detailed system description, development strategy, interface design, software engineering, and a thorough analysis and evaluation.Comment: 7 pages, 11 figur

Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface

Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this paper, we present design details of a programmable passive SoC in compliance with ISO 15693/NFC5 standard for biomedical applications. The integrated system consists of a 32-bit microcontroller, a sensor readout circuit, a 12-bit SAR type ADC, 16 kB RAM, 16 kB ROM and other digital peripherals. The design is implemented in a 0.18 μ m CMOS technology and used a die area of 1.52 mm × 3.24 mm. The simulated maximum power consumption of the analog block is 592 μ W. The number of external components required by the SoC is limited to an external memory device, sensors, antenna and some passive components. The external memory device contains the application specific firmware. Based on the application, the firmware can be modified accordingly. The SoC design is suitable for medical implants to measure physiological parameters like temperature, pressure or ECG. As an application example, the authors have proposed a bioimplant to measure arterial blood pressure for patients suffering from Peripheral Artery Disease (PAD)

Flexible Evaluation of RFID System Parameters using Rapid Prototyping

Abstract-Today's RFID systems are dependent on a wide range of different parameters, that influence the overall performance. Such system parameters can for example be the selected data rate, encoding scheme, modulation setting, transmit power or different hardware configurations, like one or two antenna scenarios. Furthermore, it is often desired to optimise several performance goals, like read-out range, read-out quality, throughput, etc., which are often contradicting each other. In order to achieve a desired performance of an RFID system, it is essential to understand the influences of the individual parameters of interest and their interconnection. Due to the multitude, wide range and interdependencies of influencing factors, this however is a complex task. Simulations offer insights in these relations but rely on the correct modeling of the dependencies of-and between the parameters. With our established prototyping system for RFID, we are able to flexibly and accurately explore the influence and interconnection of such parameters in a wide range on a basis of real-time measurements. Results on the evaluation of read-out quality depending on the transmit power and the data rate are presented

Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments

RCE (Resource Constrained Environment) is known for its stringent hardware design requirements. With the rise of Internet of Things (IoT), low-complexity and low-area designs are becoming prominent in the face of complex security threats. Two low-complexity, low-area cryptographic processors based on the ultimate reduced instruction set computer (URISC) are created to provide security features for wireless visual sensor networks (WVSN) by using field-programmable gate array (FPGA) based visual processors typically used in RCEs. The first processor is the Two Instruction Set Computer (TISC) running the Skipjack cipher. To improve security, a Compact Instruction Set Architecture (CISA) processor running the full AES with modified S-Box was created. The modified S-Box achieved a gate count reduction of 23% with no functional compromise compared to Boyar’s. Using the Spartan-3L XC3S1500L-4-FG320 FPGA, the implementation of the TISC occupies 71 slices and 1 block RAM. The TISC achieved a throughput of 46.38 kbps at a stable 24MHz clock. The CISA which occupies 157 slices and 1 block RAM, achieved a throughput of 119.3 kbps at a stable 24MHz clock. The CISA processor is demonstrated in two main applications, the first in a multilevel, multi cipher architecture (MMA) with two modes of operation, (1) by selecting cipher programs (primitives) and sharing crypto-blocks, (2) by using simple authentication, key renewal schemes, and showing perceptual improvements over direct AES on images. The second application demonstrates the use of the CISA processor as part of a selective encryption architecture (SEA) in combination with the millions instructions per second set partitioning in hierarchical trees (MIPS SPIHT) visual processor. The SEA is implemented on a Celoxica RC203 Vertex XC2V3000 FPGA occupying 6251 slices and a visual sensor is used to capture real world images. Four images frames were captured from a camera sensor, compressed, selectively encrypted, and sent over to a PC environment for decryption. The final design emulates a working visual sensor, from on node processing and encryption to back-end data processing on a server computer

IMPLEMENTATION OF THERMOELECTRIC GENERATOR MODULE AS EXTERNAL ENERGY SOURCE TO RFID TAG

One of the wireless technologies available that are expanding very fast is the RFID technology. There are three (3) different types such as active, passive and semi-active RFID tag. The main concern is that the tag consumes vast amount of power due to the availability of sensors and internal electronic components in the circuitry of the tag. The goal of this project is to solve this matter by finding suitable approach for supplying power externally to the tag. At present RFID tag uses battery to operate and this battery does not last long due to low capacity. From the literature review and detailed research, it is found that the Thermoelectric Generator (TEG) is the best approach to be implemented to solve the issue. TEG is used to harvest heat energy from human body and convert it to electrical energy and directly supply to the tag. Other option such as the replacement of normal battery to rechargeable battery is also in consideration. This will enable a cutting cost of maintenance of the tag. It also shall increase the performance of the active RFID tag

Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments

RCE (Resource Constrained Environment) is known for its stringent hardware design requirements. With the rise of Internet of Things (IoT), low-complexity and low-area designs are becoming prominent in the face of complex security threats. Two low-complexity, low-area cryptographic processors based on the ultimate reduced instruction set computer (URISC) are created to provide security features for wireless visual sensor networks (WVSN) by using field-programmable gate array (FPGA) based visual processors typically used in RCEs. The first processor is the Two Instruction Set Computer (TISC) running the Skipjack cipher. To improve security, a Compact Instruction Set Architecture (CISA) processor running the full AES with modified S-Box was created. The modified S-Box achieved a gate count reduction of 23% with no functional compromise compared to Boyar’s. Using the Spartan-3L XC3S1500L-4-FG320 FPGA, the implementation of the TISC occupies 71 slices and 1 block RAM. The TISC achieved a throughput of 46.38 kbps at a stable 24MHz clock. The CISA which occupies 157 slices and 1 block RAM, achieved a throughput of 119.3 kbps at a stable 24MHz clock. The CISA processor is demonstrated in two main applications, the first in a multilevel, multi cipher architecture (MMA) with two modes of operation, (1) by selecting cipher programs (primitives) and sharing crypto-blocks, (2) by using simple authentication, key renewal schemes, and showing perceptual improvements over direct AES on images. The second application demonstrates the use of the CISA processor as part of a selective encryption architecture (SEA) in combination with the millions instructions per second set partitioning in hierarchical trees (MIPS SPIHT) visual processor. The SEA is implemented on a Celoxica RC203 Vertex XC2V3000 FPGA occupying 6251 slices and a visual sensor is used to capture real world images. Four images frames were captured from a camera sensor, compressed, selectively encrypted, and sent over to a PC environment for decryption. The final design emulates a working visual sensor, from on node processing and encryption to back-end data processing on a server computer

Development and Implementation of a Smart Parking Spot Allocation System Based on the User’s Category and Priority using Verilog HDL

Finding parking spots for automobiles is a major issue in many large and congested cities. Usually, drivers lose time searching for parking spots, especially during peak hours, which increases traffic congestion and makes drivers frustrated and annoyed. Large building parking areas could also become dangerous to women, pregnant women, and the elderly, as several criminal cases in the parking area, were reported. In this project, a prototype of a smart parking spot allocation system based on the user’s category and priority was developed. The choice of user categories is people with disabilities (OKU), pregnant women/elderly, women, and normal users. The highest priority is assigned to OKU, followed by pregnant women/elderly, followed by women and the lowest priority is assigned to normal users. The parking spots for the highest priority category are placed near building entrances such as mall entrances. The controller for the automatic parking spot allocation system was developed using Verilog HDL code and the prototype was implemented on FPGA DE2-115. The controller is programmed to process the user’s category which is selected by the user at the second entrance and assign a specific parking spot number according to the category’s priority. The prototype was tested with multiple parking spots condition with different user inputs for different user categories. The system was able to allocate parking spots based on the user’s category depending on the parking spot available for the selected category with 75% out of 12 tests correct. However, all 12 tests, or 100% recorded accurate allocation based on the expected output of the system design. In a conclusion, this proposed system would be able to cater to the issue of finding parking spots hence directly avoiding traffic congestion and frustration among users. In addition, this system can indirectly reduce crime cases in the parking area due to parking spaces that prioritize categories of users needing to be parked near the entrance