An assessment of RTN-induced threshold voltage jitter

Power consumption is a key issue especially for the edge devices/units in an IoT system. Lowering operation voltage is an effective way to reduce power. As the overdrive voltage, Vg-Vth, becomes smaller, the device is more vulnerable to threshold voltage jitters. One source for the jitter is Random Telegraph Noises (RTN), which cause a fluctuation in both drain current, ΔId, and threshold voltage, ΔVth. Early works on RTN were focused on measuring ΔId and then evaluate ΔVth from ΔId/gm, where gm is transconductance. The accuracy of ΔVth obtained in this way is not known. The objective of this work is to assess its accuracy by comparing it with the ΔVth directly measured from pulse Id-Vg. It will be shown that the correlation between these two is poor, so that ΔVth must not be evaluated from ΔId/gm. This is caused by the device-specific localized current distribution near the threshold

An assessment of the statistical distribution of Random Telegraph Noise Time Constants

As transistor sizes are downscaled, a single trapped charge has a larger impact on smaller devices and the Random Telegraph Noise (RTN) becomes increasingly important. To optimize circuit design, one needs assessing the impact of RTN on the circuit and this can only be accomplished if there is an accurate statistical model of RTN. The dynamic Monte Carlo modelling requires the statistical distribution functions of both the amplitude and the capture/emission time (CET) of traps. Early works were focused on the amplitude distribution and the experimental data of CETs were typically too limited to establish their statistical distribution reliably. In particular, the time window used has been often small, e.g. 10 sec or less, so that there are few data on slow traps. It is not known whether the CET distribution extracted from such a limited time window can be used to predict the RTN beyond the test time window. The objectives of this work are three fold: to provide the long term RTN data and use them to test the CET distributions proposed by early works; to propose a methodology for characterizing the CET distribution for a fabrication process efficiently; and, for the first time, to verify the long term prediction capability of a CET distribution beyond the time window used for its extraction

Flash Memory Devices

Flash memory devices have represented a breakthrough in storage since their inception in the mid-1980s, and innovation is still ongoing. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB sticks, cards, but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation, namely the 3D architecture. Today “3D” means that multiple layers of memory cells are manufactured within the same piece of silicon, easily reaching a terabit capacity. So far, Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts are based on "charge trap" cells. In summary, flash memory devices represent the largest landscape of storage devices, and we expect more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications such as AI and security enforcement

Characterisation and modelling of Random Telegraph Noise in nanometre devices

The power consumption of digital circuits is proportional to the square of operation voltage and the demand for low power circuits reduces the operation voltage towards the threshold of MOSFETs. A weak voltage signal makes circuits vulnerable to noise and the optimization of circuit design requires an accurate noise model. RTN is the dominant noise for modern CMOS technologies. This research focuses on the instability induced by Random Telegraph Noise (RTN) in nano-devices for low power applications, such as the Internet of Things (IoT). RTN is a stochastic noise that can be observed in the drain/gate current of a device when traps capture and emit electrons or holes. The impact of RTN instabilities in devices has been widely investigated. Although progress has been made, the understanding of RTN instabilities remains incomplete and many issues are unresolved. This work focuses on developing a statistical model for characterising, modelling and analysing of the impact of RTN on MOSFET performance, as well as to study the prediction for long-term RTN impact on real circuits. As transistor sizes are downscaled, a single trapped charge has a larger impact and RTN becomes increasingly important. To optimize circuit design, one needs to assess the impact of RTN on circuits, which can only be accomplished if there is an accurate statistical model of RTN. The dynamic Monte Carlo modelling requires the statistical distribution functions of both the amplitude and the capture/emission time (CET) of traps. Early works were focused on the amplitude distribution and the experimental data of CETs has been too limited to establish their statistical distribution reliably. In particular, the time window used has often been small, e.g. 10 sec or less, so that there is little data on slow traps. It is not known whether the CET distribution extracted from such a limited time window can be used to predict the RTN beyond the test time window. The first contribution of this work is three-fold: to provide long-term RTN data and use it to test the CET distributions proposed by early works; to propose a methodology for characterising the CET distribution for a fabrication process efficiently; and, for the first time, to verify the long-term prediction capability of a CET distribution beyond the time window used for its extraction. On the statistical distributions of RTN amplitude, three different distributions were proposed by early works: Lognormal, Exponential, and Gumbel distributions. They give substantially different RTN predictions and agreement has not been reached on which distribution should be used, calling the modelling accuracy into question. The second contribution of this work is to assess the accuracy of these three distributions and to explore other distributions for better accuracy. A novel criterion has been proposed for selecting distributions, which requires a monotonic reduction of modelling errors with increasing number of traps. The three existing distributions do not meet this criterion and thirteen other distributions are explored. It is found that the Generalized Extreme Value (GEV) distribution has the lowest error and meets the new criterion. Moreover, to reduce modelling errors, early works used bimodal Lognormal and Exponential distributions, which have more fitting parameters. Their errors, however, are still higher than those of the monomodal GEV distribution. GEV has a long distribution tail and predicts substantially worse RTN impact. The project highlights the uncertainty in predicting the RTN distribution tail by different statistical models. The last contribution of the project is studying the impact of different gate biases on RTN distributions. At two different gate voltage conditions: one close to threshold voltage |Vth| and the other under operating conditions, it is found that the RTN amplitude follows different distributions. At operating voltage condition, Lognormal distribution has the lowest error for RTN amplitude distribution in comparison with other distributions. The amplitude distribution at close to |Vth| has a longer tail compared with the distribution tail at operating voltage. However, RTN capture/emission time distribution is not impacted by gate bias and follows Log-uniform distribution

Experimental Characterization of Random Telegraph Noise and Hot Carrier Aging of Nano-scale MOSFETs

One of the emerging challenges in the scaling of MOSFETs is the reliability of ultra-thin gate dielectrics. Various sources can cause device aging, such as hot carrier aging (HCA), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and time dependent device breakdown (TDDB). Among them, hot carrier aging (HCA) has attracted much attention recently, because it is limiting the device lifetime. As the channel length of MOSFETs becomes smaller, the lateral electrical field increases and charge carriers become sufficiently energetic (“hot”) to cause damage to the device when they travel through the space charge region near the drain. Unlike aging that causes device parameters, such as threshold voltage, to drift in one direction, nano-scale devices also suffer from Random Telegraph Noise (RTN), where the current can fluctuate under fixed biases. RTN is caused by capturing/emitting charge carriers from/to the conduction channel. As the device sizes are reduced to the nano-meters, a single trap can cause substantial fluctuation in the current and threshold voltage. Although early works on HCA and RTN have improved the understanding, many issues remain unresolved and the aim of this project is to address these issues. The project is broadly divided into three parts: (i) an investigation on the HCA kinetics and how to predict HCA-induced device lifetime, (ii) a study of the interaction between HCA and RTN, and (iii) developing a new technique for directly measuring the RTN-induced jitter in the threshold voltage. To predict the device lifetime, a reliable aging kinetics is indispensable. Although early works show that HCA follows a power law, there are uncertainties in the extraction of the time exponent, making the prediction doubtful. A systematic experimental investigation was carried out in Chapter 4 and both the stress conditions and measurement parameters were carefully selected. It was found that the forward saturation current, commonly used in early work for monitoring HCA, leads to an overestimation of time exponents, because part of the damaged region is screened off by the space charges near the drain. Another source of errors comes from the inclusion of as-grown defects in the aging kinetics, which is not caused by aging. This leads to an underestimation of the time exponent. After correcting these errors, a reliable HCA kinetics is established and its predictive capability is demonstrated. There is confusion on how HCA and RTN interact and this is researched into in Chapter 5. The results show that for a device of average RTN, HCA only has a modest impact on RTN. RTN can either increase or decrease after HCA, depending on whether the local current under the RTN traps is rising or reducing. For a device of abnormally high RTN, RTN reduces substantially after HCA and the mechanism for this reduction is explored. The RTN-induced threshold voltage jitter, ∆Vth, is difficult to measure, as it is typically small and highly dynamic. Early works estimate this ∆Vth from the change in drain current and the accuracy of this estimation is not known. Chapter 6 focuses on developing a new ‘Trigger-When-Charged’ technique for directly measuring the RTN-induced ∆Vth. It will be shown that early works overestimate ∆Vth by a factor of two and the origin of this overestimation is investigated. This thesis consists of seven chapters. Chapter 1 introduces the project and its objectives. A literature review is given in Chapter 2. Chapter 3 covers the test facilities, measurement techniques, and devices used in this project. The main experimental results and analysis are given in Chapters 4-6, as described above. Finally, Chapter 7 concludes the project and discusses future works

Hardware implementation of a true random number generator integrating a hexagonal boron nitride memristor with a commercial microcontroller

The development of the internet-of-things requires cheap, light, small and reliable true random number generator (TRNG) circuits to encrypt the data—generated by objects or humans—before transmitting them. However, all current solutions consume too much power and require a relatively large battery, hindering the integration of TRNG circuits on most objects. Here we fabricated a TRNG circuit by exploiting stable random telegraph noise (RTN) current signals produced by memristors made of two-dimensional (2D) multi-layered hexagonal boron nitride (h-BN) grown by chemical vapor deposition and coupled with inkjet-printed Ag electrodes. When biased at small constant voltages (≤70 mV), the Ag/h-BN/Ag memristors exhibit RTN signals with very low power consumption (∼5.25 nW) and a relatively high current on/off ratio (∼2) for long periods (>1 hour). We constructed TRNG circuits connecting an h-BN memristor to a small, light and cheap commercial microcontroller, producing a highly-stochastic, high-throughput signal (up to 7.8 Mbit s−1) even if the RTN at the input gets interrupted for long times up to 20 s, and if the stochasticity of the RTN signal is reduced. Our study presents the first full hardware implementation of 2Dmaterial- based TRNGs, enabled by the unique stability and figures of merit of the RTN signals in h-BN based memristors.Ministry of Science and Technology, China 2019YFE0124200 2018YFE0100800National Natural Science Foundation of China (NSFC) 61874075Collaborative Innovation Centre of Suzhou Nano Science and TechnologyPriority Academic Program Development of Jiangsu Higher Education Institutions111 Project from the State Administration of Foreign Experts Affairs of ChinaKing Abdullah University of Science & TechnologyMinisterio de Ciencia, Tecnologia e Innovacion (MINCyT) PICT 2016/0579 PME 2015-0196 PICTE 2018-0192 UTN-FRBA CCUTIBA4764TC MATUNBA4936 CCUTNBA5182 CCUTNBA661

Hardware implementation of a true random number generator integrating a hexagonal boron nitride memristor with a commercial microcontroller

The development of the internet-of-things requires cheap, light, small and reliable true random number generator (TRNG) circuits to encrypt the data-generated by objects or humans-before transmitting them. However, all current solutions consume too much power and require a relatively large battery, hindering the integration of TRNG circuits on most objects. Here we fabricated a TRNG circuit by exploiting stable random telegraph noise (RTN) current signals produced by memristors made of two-dimensional (2D) multi-layered hexagonal boron nitride (h-BN) grown by chemical vapor deposition and coupled with inkjet-printed Ag electrodes. When biased at small constant voltages (<= 70 mV), the Ag/h-BN/Ag memristors exhibit RTN signals with very low power consumption (similar to 5.25 nW) and a relatively high current on/off ratio (similar to 2) for long periods (>1 hour). We constructed TRNG circuits connecting an h-BN memristor to a small, light and cheap commercial microcontroller, producing a highly-stochastic, high-throughput signal (up to 7.8 Mbit s(-1)) even if the RTN at the input gets interrupted for long times up to 20 s, and if the stochasticity of the RTN signal is reduced. Our study presents the first full hardware implementation of 2D-material-based TRNGs, enabled by the unique stability and figures of merit of the RTN signals in h-BN based memristors

On the accuracy in modelling the statistical distribution of Random Telegraph Noise Amplitude

The power consumption of digital circuits is proportional to the square of operation voltage and the demand for low power circuits reduces the operation voltage towards the threshold of MOSFETs. A weak voltage signal makes circuits vulnerable to noise and the optimization of circuit design requires modelling noise. Random Telegraph Noise (RTN) is the dominant noise for modern CMOS technologies and Monte Carlo modelling has been used to assess its impact on circuits. This requires statistical distributions of RTN amplitude and three different distributions were proposed by early works: Lognormal, Exponential, and Gumbel distributions. They give substantially different RTN predictions and agreement has not been reached on which distribution should be used, calling the modelling accuracy into questions. The objective of this work is to assess the accuracy of these three distributions and to explore other distributions for better accuracy. A novel criterion has been proposed for selecting distributions, which requires a monotonic reduction of modelling errors with increasing number of traps. The three existing distributions do not meet this criterion and thirteen other distributions are explored. It is found that the Generalized Extreme Value (GEV) distribution has the lowest error and meet the new criterion. Moreover, to reduce modelling errors, early works used bimodal Lognormal and Exponential distributions, which have more fitting parameters. Their errors, however, are still higher than those of the monomodal GEV distribution. GEV has a long distribution tail and predicts substantially worse RTN impact. The work highlights the uncertainty in predicting the RTN distribution tail by different statistical models

Space Shuttle program communication and tracking systems interface analysis

The Space Shuttle Program Communications and Tracking Systems Interface Analysis began April 18, 1983. During this time, the shuttle communication and tracking systems began flight testing. Two areas of analysis documented were a result of observations made during flight tests. These analyses involved the Ku-band communication system. First, there was a detailed analysis of the interface between the solar max data format and the Ku-band communication system including the TDRSS ground station. The second analysis involving the Ku-band communication system was an analysis of the frequency lock loop of the Gunn oscillator used to generate the transmit frequency. The stability of the frequency lock loop was investigated and changes to the design were reviewed to alleviate the potential loss of data due the loop losing lock and entering the reacquisition mode. Other areas of investigation were the S-band antenna analysis and RF coverage analysis